1/*
2 * Copyright 2022-2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <nxp/rw/RW612-pinctrl.h>
8
9&pinctrl {
10	pinmux_flexcomm3_usart: pinmux_flexcomm3_usart {
11		group0 {
12			pinmux = <IO_MUX_FC3_USART_DATA>;
13			slew-rate = "normal";
14		};
15	};
16
17	pinmux_flexcomm0_usart: pinmux_flexcomm0_usart {
18		group0 {
19			pinmux = <IO_MUX_FC0_USART_DATA>;
20			slew-rate = "normal";
21		};
22	};
23
24	pinmux_flexcomm0_spi: pinmux_flexcomm0_spi {
25		group0 {
26			pinmux = <IO_MUX_FC0_SPI_SS0_IO0>,
27				<IO_MUX_FC0_SPI_SS0_IO2>,
28				<IO_MUX_FC0_SPI_SS0_IO3>,
29				<IO_MUX_FC0_SPI_SS0_IO4>;
30			slew-rate = "ultra";
31		};
32	};
33
34	pinmux_flexcomm2_i2c: pinmux_flexcomm2_i2c {
35		group0 {
36			pinmux = <IO_MUX_FC2_I2C_16_17>;
37			slew-rate = "normal";
38			bias-pull-up;
39		};
40	};
41
42	pinmux_dmic0: pinmux_dmic0 {
43		group0 {
44			pinmux = <IO_MUX_PDM_IO51
45				IO_MUX_PDM_IO52
46				IO_MUX_PDM_IO53
47				IO_MUX_PDM_IO54>;
48			slew-rate = "fast";
49		};
50	};
51
52	pinmux_lcdic: pinmux_lcdic {
53		group0 {
54			pinmux = <IO_MUX_LCD_SPI_IO44>,
55				<IO_MUX_LCD_SPI_IO45>,
56				<IO_MUX_LCD_SPI_IO46>,
57				<IO_MUX_LCD_SPI_IO47>,
58				<IO_MUX_LCD_SPI_IO48>,
59				<IO_MUX_LCD_SPI_IO49>;
60			slew-rate = "ultra";
61		};
62	};
63
64	pinmux_flexspi: pinmux_flexspi {
65		group0 {
66			pinmux = <IO_MUX_QUAD_SPI_FLASH_IO28
67				IO_MUX_QUAD_SPI_FLASH_IO30
68				IO_MUX_QUAD_SPI_FLASH_IO31
69				IO_MUX_QUAD_SPI_FLASH_IO32
70				IO_MUX_QUAD_SPI_FLASH_IO33
71				IO_MUX_QUAD_SPI_FLASH_IO34>;
72			slew-rate = "ultra";
73		};
74
75		group1 {
76			pinmux = <IO_MUX_QUAD_SPI_FLASH_IO29>;
77			slew-rate = "ultra";
78			bias-pull-down;
79		};
80
81		group2 {
82			pinmux = <IO_MUX_QUAD_SPI_PSRAM_IO35
83				IO_MUX_QUAD_SPI_PSRAM_IO36
84				IO_MUX_QUAD_SPI_PSRAM_IO38
85				IO_MUX_QUAD_SPI_PSRAM_IO39
86				IO_MUX_QUAD_SPI_PSRAM_IO40
87				IO_MUX_QUAD_SPI_PSRAM_IO41>;
88			slew-rate = "normal";
89		};
90
91		group3 {
92			pinmux = <IO_MUX_QUAD_SPI_PSRAM_IO37>;
93			slew-rate = "normal";
94			bias-pull-down;
95		};
96	};
97
98	pinmux_enet: pinmux_enet {
99		group0 {
100			pinmux = <IO_MUX_ENET_CLK
101				IO_MUX_ENET_RX
102				IO_MUX_ENET_TX
103				IO_MUX_GPIO21
104				IO_MUX_GPIO55>;
105			slew-rate = "fast";
106		};
107	};
108
109	pinmux_mdio: pinmux_mdio {
110		group0 {
111			pinmux = <IO_MUX_ENET_MDIO>;
112			slew-rate = "fast";
113		};
114	};
115};
116