1/*
2 * Copyright (c) 2023 Google LLC.
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6/dts-v1/;
7#include <mem.h>
8#include <xtensa/xtensa.dtsi>
9
10/ {
11	model = "nxp_adsp_rt595";
12	compatible = "nxp";
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			device_type = "cpu";
20			compatible = "cdns,tensilica-xtensa-lx6";
21			reg = <0>;
22		};
23	};
24
25	sram0: memory@0 {
26		#address-cells = <1>;
27		#size-cells = <1>;
28		device_type = "memory";
29		compatible = "mmio-sram";
30		/* Reserve first 512kB of shared memory for ADSP. */
31		reg = <0x0 DT_SIZE_K(512)>;
32		/* Reset section must always be at 0 and at least 1kB. */
33		adsp_reset: memory@0 {
34			reg = <0x0 DT_SIZE_K(1)>;
35		};
36		/* Code and data sections can be moved around and resized if needed. */
37		adsp_text: memory@400 {
38			reg = <0x400 DT_SIZE_K(255)>;
39		};
40		/* On RT595 ADSP shared RAM is mapped at offset 0 on the code bus and at
41		 * offset 0x800000 on the data bus.
42		 */
43		adsp_data: memory@840000 {
44			reg = <0x840000 DT_SIZE_K(256)>;
45		};
46	};
47
48	chosen {
49		zephyr,sram = &adsp_data;
50	};
51};
52