1.. _lpcxpresso55s69: 2 3NXP LPCXPRESSO55S69 4################### 5 6Overview 7******** 8 9The LPCXpresso55S69 development board provides the ideal platform for evaluation 10of and development with the LPC55S6x MCU based on the Arm® Cortex®-M33 11architecture. The board includes a high performance onboard debug probe, audio 12subsystem, and accelerometer, with several options for adding off-the-shelf 13add-on boards for networking, sensors, displays, and other interfaces. 14 15.. image:: lpcxpresso55s69.jpg 16 :align: center 17 :alt: LPCXPRESSO55S69 18 19Hardware 20******** 21 22- LPC55S69 dual core Arm Cortex-M33 microcontroller running at up to 100 MHz 23- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP and SEGGER J-Link 24 protocol options 25- UART and SPI port bridging from LPC55S69 target to USB via the onboard debug 26 probe 27- Hardware support for external debug probe 28- 3 x user LEDs, plus Reset, ISP (3) and user buttons 29- Micro SD card slot (4-bit SDIO) 30- NXP MMA8652FCR1 accelerometer 31- Stereo audio codec with line in/out 32- High and full speed USB ports with micro A/B connector for host or device 33 functionality 34- MikroEletronika Click expansion option 35- LPCXpresso-V3 expansion option compatible with Arduino UNO 36- PMod compatible expansion / host connector 37 38For more information about the LPC55S69 SoC and LPCXPRESSO55S69 board, see: 39 40- `LPC55S69 SoC Website`_ 41- `LPC55S69 Datasheet`_ 42- `LPC55S69 Reference Manual`_ 43- `LPCXPRESSO55S69 Website`_ 44- `LPCXPRESSO55S69 User Guide`_ 45- `LPCXPRESSO55S69 Schematics`_ 46- `LPCXPRESSO55S69 Debug Firmware`_ 47 48Supported Features 49================== 50 51NXP considers the LPCXpresso55S69 as the superset board for the LPC55xx 52series of MCUs. This board is a focus for NXP's Full Platform Support for 53Zephyr, to better enable the entire LPC55xx series. NXP prioritizes enabling 54this board with new support for Zephyr features. The lpcxpresso55s69 board 55configuration supports the following hardware features: 56 57+-----------+------------+-------------------------------------+ 58| Interface | Controller | Driver/Component | 59+===========+============+=====================================+ 60| NVIC | on-chip | nested vector interrupt controller | 61+-----------+------------+-------------------------------------+ 62| SYSTICK | on-chip | systick | 63+-----------+------------+-------------------------------------+ 64| IOCON | on-chip | pinmux | 65+-----------+------------+-------------------------------------+ 66| GPIO | on-chip | gpio | 67+-----------+------------+-------------------------------------+ 68| I2C | on-chip | i2c | 69+-----------+------------+-------------------------------------+ 70| SPI | on-chip | spi | 71+-----------+------------+-------------------------------------+ 72| USART | on-chip | serial port-polling; | 73| | | serial port-interrupt | 74+-----------+------------+-------------------------------------+ 75| WWDT | on-chip | windowed watchdog timer | 76+-----------+------------+-------------------------------------+ 77| TrustZone | on-chip | Trusted Firmware-M | 78+-----------+------------+-------------------------------------+ 79| ADC | on-chip | adc | 80+-----------+------------+-------------------------------------+ 81| CLOCK | on-chip | clock_control | 82+-----------+------------+-------------------------------------+ 83| MAILBOX | on-chip | ipm | 84+-----------+------------+-------------------------------------+ 85| HWINFO | on-chip | Unique device serial number | 86+-----------+------------+-------------------------------------+ 87| USB HS | on-chip | USB High Speed device | 88+-----------+------------+-------------------------------------+ 89| USB FS | on-chip | USB Full Speed device | 90+-----------+------------+-------------------------------------+ 91| COUNTER | on-chip | counter | 92+-----------+------------+-------------------------------------+ 93| I2S | on-chip | i2s | 94+-----------+------------+-------------------------------------+ 95| PWM | on-chip | pwm | 96+-----------+------------+-------------------------------------+ 97| RNG | on-chip | entropy; | 98| | | random | 99+-----------+------------+-------------------------------------+ 100| IAP | on-chip | flash programming | 101+-----------+------------+-------------------------------------+ 102| SDIF | on-chip | sdhc | 103+-----------+------------+-------------------------------------+ 104| DMA | on-chip | dma (on CPU0) | 105+-----------+------------+-------------------------------------+ 106 107Targets available 108================== 109 110The default configuration file 111:zephyr_file:`boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig` 112only enables the first core. 113CPU0 is the only target that can run standalone. 114 115- *lpcxpresso55s69/lpc55s69/cpu0* secure (S) address space for CPU0 116- *lpcxpresso55s69/lpc55s69/cpu0/ns* non-secure (NS) address space for CPU0 117- *lpcxpresso55s69/lpc55s69/cpu1* CPU1 target, no security extensions 118 119NS target for CPU0 does not work correctly without a secure image to configure 120the system, then hand execution over to the NS environment. To enable a secure 121image, run any of the ``tfm_integration`` samples. When using the NS target 122``CONFIG_BUILD_WITH_TFM`` is always enabled to ensure that a valid S image is 123included during the build process. 124 125CPU1 does not work without CPU0 enabling it. 126To enable it, run one of the following samples in ``subsys\ipc``: 127 128- ``ipm_mcux`` 129- ``openamp`` 130 131Connections and IOs 132=================== 133 134The LPC55S69 SoC has IOCON registers, which can be used to configure the 135functionality of a pin. 136 137+---------+-----------------+----------------------------+ 138| Name | Function | Usage | 139+=========+=================+============================+ 140| PIO0_26 | SPI | SPI MOSI | 141+---------+-----------------+----------------------------+ 142| PIO0_27 | USART | USART TX | 143+---------+-----------------+----------------------------+ 144| PIO0_29 | USART | USART RX | 145+---------+-----------------+----------------------------+ 146| PIO0_30 | USART | USART TX | 147+---------+-----------------+----------------------------+ 148| PIO1_1 | SPI | SPI SSEL | 149+---------+-----------------+----------------------------+ 150| PIO1_2 | SPI | SPI SCK | 151+---------+-----------------+----------------------------+ 152| PIO1_3 | SPI | SPI MISO | 153+---------+-----------------+----------------------------+ 154| PIO1_4 | GPIO | RED LED | 155+---------+-----------------+----------------------------+ 156| PIO1_6 | GPIO | BLUE_LED | 157+---------+-----------------+----------------------------+ 158| PIO1_7 | GPIO | GREEN LED | 159+---------+-----------------+----------------------------+ 160| PIO1_20 | I2C | I2C SCL | 161+---------+-----------------+----------------------------+ 162| PIO1_21 | I2C | I2C SDA | 163+---------+-----------------+----------------------------+ 164| PIO1_24 | USART | USART RX | 165+---------+-----------------+----------------------------+ 166| PIO0_20 | I2S | I2S DATAOUT | 167+---------+-----------------+----------------------------+ 168| PIO0_19 | I2S | I2S TX WS | 169+---------+-----------------+----------------------------+ 170| PIO0_21 | I2S | I2S TX SCK | 171+---------+-----------------+----------------------------+ 172| PIO1_13 | I2S | I2S DATAIN | 173+---------+-----------------+----------------------------+ 174| PIO0_15 | SCT0_OUT2 | PWM | 175+---------+-----------------+----------------------------+ 176| PIO0_24 | SD0_D0 | SDHC | 177+---------+-----------------+----------------------------+ 178| PIO0_25 | SD0_D1 | SDHC | 179+---------+-----------------+----------------------------+ 180| PIO0_31 | SD0_D2 | SDHC | 181+---------+-----------------+----------------------------+ 182| PIO0_7 | SD0_CLK | SDHC | 183+---------+-----------------+----------------------------+ 184| PIO0_8 | SD0_CMD | SDHC | 185+---------+-----------------+----------------------------+ 186| PIO0_9 | SD0_POW_EN | SDHC | 187+---------+-----------------+----------------------------+ 188| PIO1_0 | SD0_D3 | SDHC | 189+---------+-----------------+----------------------------+ 190 191Memory mappings 192=============== 193 194There are multiple memory configurations, they all start from the 195MCUboot partitioning which looks like the table below 196 197+----------+------------------+---------------------------------+ 198| Name | Address[Size] | Comment | 199+==========+==================+=================================+ 200| boot | 0x00000000[32K] | Bootloader | 201+----------+------------------+---------------------------------+ 202| slot0 | 0x00008000[160k] | Image that runs after boot | 203+----------+------------------+---------------------------------+ 204| slot0_ns | 0x00030000[96k] | Second image, core 1 or NS | 205+----------+------------------+---------------------------------+ 206| slot1 | 0x00048000[160k] | Updates slot0 image | 207+----------+------------------+---------------------------------+ 208| slot1_ns | 0x00070000[96k] | Updates slot0_ns image | 209+----------+------------------+---------------------------------+ 210| storage | 0x00088000[50k] | File system, persistent storage | 211+----------+------------------+---------------------------------+ 212 213See below examples of how this partitioning is used 214 215Trusted Execution 216***************** 217 218+-----------+------------------+--------------------+ 219| Memory | Address[Size] | Comment | 220+===========+==================+====================+ 221| MCUboot | 0x00000000[32K] | Secure bootloader | 222+-----------+------------------+--------------------+ 223| TFM_S | 0x00008000[160k] | Secure image | 224+-----------+------------------+--------------------+ 225| Zephyr_NS | 0x00030000[96k] | Non-Secure image | 226+-----------+------------------+--------------------+ 227| storage | 0x00088000[50k] | Persistent storage | 228+-----------+------------------+--------------------+ 229 230+----------------+------------------+-------------------+ 231| RAM | Address[Size] | Comment | 232+================+==================+===================+ 233| secure_ram | 0x20000000[136k] | Secure memory | 234+----------------+------------------+-------------------+ 235| non_secure_ram | 0x20022000[136k] | Non-Secure memory | 236+----------------+------------------+-------------------+ 237 238Dual Core samples 239***************** 240 241+--------+------------------+----------------------------+ 242| Memory | Address[Size] | Comment | 243+========+==================+============================+ 244| CPU0 | 0x00000000[630K] | CPU0, can access all flash | 245+--------+------------------+----------------------------+ 246| CPU1 | 0x00030000[96k] | CPU1, has no MPU | 247+--------+------------------+----------------------------+ 248 249+-------+------------------+-----------------------+ 250| RAM | Address[Size] | Comment | 251+=======+==================+=======================+ 252| sram0 | 0x20000000[64k] | CPU0 memory | 253+-------+------------------+-----------------------+ 254| sram3 | 0x20030000[64k] | CPU1 memory | 255+-------+------------------+-----------------------+ 256| sram4 | 0x20040000[16k] | Mailbox/shared memory | 257+-------+------------------+-----------------------+ 258 259System Clock 260============ 261 262The LPC55S69 SoC is configured to use PLL1 clocked from the external 16MHz 263crystal, running at 144MHz as a source for the system clock. When the flash 264controller is enabled, the core clock will be reduced to 96MHz. The application 265may reconfigure clocks after initialization, provided that the core clock is 266always set to 96MHz when flash programming operations are performed. 267 268Serial Port 269=========== 270 271The LPC55S69 SoC has 8 FLEXCOMM interfaces for serial communication. One is 272configured as USART for the console and the remaining are not used. 273 274Programming and Debugging 275************************* 276 277Build and flash applications as usual (see :ref:`build_an_application` and 278:ref:`application_run` for more details). 279 280Configuring a Debug Probe 281========================= 282 283A debug probe is used for both flashing and debugging the board. This board is 284configured by default to use the LPC-Link2 CMSIS-DAP Onboard Debug Probe, 285however the :ref:`pyocd-debug-host-tools` does not yet support this probe so you 286must reconfigure the board for one of the following debug probes instead. 287 288:ref:`lpclink2-jlink-onboard-debug-probe` 289----------------------------------------- 290 291Install the :ref:`jlink-debug-host-tools` and make sure they are in your search 292path. 293 294Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program 295the J-Link firmware. Please make sure you have the latest firmware for this 296board. 297 298:ref:`lpclink2-cmsis-onboard-debug-probe` 299----------------------------------------- 300 301 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. 302 2. To update the debug firmware, please follow the instructions on `LPCXPRESSO55S69 Debug Firmware` 303 304:ref:`opensda-daplink-onboard-debug-probe` 305------------------------------------------ 306 307PyOCD support for this board is ongoing and not yet available. 308To use DAPLink's flash memory programming on this board, follow the instructions 309for `updating LPCXpresso firmware`_. 310 311Configuring a Console 312===================== 313 314Connect a USB cable from your PC to P6, and use the serial terminal of your choice 315(minicom, putty, etc.) with the following settings: 316 317- Speed: 115200 318- Data: 8 bits 319- Parity: None 320- Stop bits: 1 321 322Flashing 323======== 324 325Here is an example for the :ref:`hello_world` application. This example uses the 326:ref:`jlink-debug-host-tools` as default. 327 328.. zephyr-app-commands:: 329 :zephyr-app: samples/hello_world 330 :board: lpcxpresso55s69/lpc55s69/cpu0 331 :goals: flash 332 333Open a serial terminal, reset the board (press the RESET button), and you should 334see the following message in the terminal: 335 336.. code-block:: console 337 338 ***** Booting Zephyr OS v1.14.0 ***** 339 Hello World! lpcxpresso55s69 340 341Building and flashing secure/non-secure with Arm |reg| TrustZone |reg| 342---------------------------------------------------------------------- 343The TF-M integration samples can be run using the 344``lpcxpresso55s69/lpc55s69/cpu0/ns`` target. To run we need to manually flash 345the resulting image (``tfm_merged.hex``) with a J-Link as follows 346(reset and erase are for recovering a locked core): 347 348 .. code-block:: console 349 350 JLinkExe -device lpc55s69 -if swd -speed 2000 -autoconnect 1 351 J-Link>r 352 J-Link>erase 353 J-Link>loadfile build/zephyr/tfm_merged.hex 354 355We need to reset the board manually after flashing the image to run this code. 356 357Building a dual-core image 358-------------------------- 359The dual-core samples are run using ``lpcxpresso55s69/lpc55s69/cpu0`` target. 360Images built for ``lpcxpresso55s69/lpc55s69/cpu1`` will be loaded from flash 361and executed on the second core when ``SECOND_CORE_MCUX`` is selected. For 362an example of building for both cores with sysbuild, see 363``samples/subsys/ipc/openamp/`` 364 365Debugging 366========= 367 368Here is an example for the :ref:`hello_world` application. This example uses the 369:ref:`jlink-debug-host-tools` as default. 370 371.. zephyr-app-commands:: 372 :zephyr-app: samples/hello_world 373 :board: lpcxpresso55s69/lpc55s69/cpu0 374 :goals: debug 375 376Open a serial terminal, step through the application in your debugger, and you 377should see the following message in the terminal: 378 379.. code-block:: console 380 381 ***** Booting Zephyr OS zephyr-v1.14.0 ***** 382 Hello World! lpcxpresso55s69 383 384.. _LPC55S69 SoC Website: 385 https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc5500-cortex-m33/high-efficiency-arm-cortex-m33-based-microcontroller-family:LPC55S6x 386 387.. _LPC55S69 Datasheet: 388 https://www.nxp.com/docs/en/nxp/data-sheets/LPC55S6x_DS.pdf 389 390.. _LPC55S69 Reference Manual: 391 https://www.nxp.com/webapp/Download?colCode=UM11126 392 393.. _LPCXPRESSO55S69 Website: 394 https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc5500-cortex-m33/lpcxpresso55s69-development-board:LPC55S69-EVK 395 396.. _LPCXPRESSO55S69 User Guide: 397 https://www.nxp.com/webapp/Download?colCode=UM11158 398 399.. _LPCXPRESSO55S69 Debug Firmware: 400 https://www.nxp.com/docs/en/application-note/AN13206.pdf 401 402.. _LPCXPRESSO55S69 Schematics: 403 https://www.nxp.com/webapp/Download?colCode=LPC55S69-SCH 404 405.. _updating LPCXpresso firmware: 406 https://os.mbed.com/teams/NXP/wiki/Updating-LPCXpresso-firmware 407
