1#
2# NXP LPCXpresso11U68 (evaluation board OM13058)
3#
4# http://www.nxp.com/board/OM13058.html
5# https://www.embeddedartists.com/products/lpc11u68-lpcxpresso/
6# https://os.mbed.com/platforms/LPCXpresso11U68/
7#
8
9# The on-board LPC-Link2 debug probe (based on a NXP LPC43xx MCU) provides
10# either a CMSIS-DAP or a J-Link interface. It depends on the version of the
11# embedded firmware. Uncomment the line corresponding to yours.
12source [find interface/cmsis-dap.cfg]
13# source [find interface/jlink.cfg]
14
15# NXP LPC11U68 Cortex-M0 with 256kB flash and 32kB + 4kB SRAM.
16set WORKAREASIZE 0x5000
17
18source [find target/lpc11xx.cfg]
19
20# This ensures that the interrupt vectors (0x0000-0x0200) are re-mapped to
21# flash after the "reset halt" command. Else the load/verify functions won't
22# work correctly.
23#
24# Table 8. System memory remap register (SYSMEMREMAP, address 0x40048000) bit
25#          description
26# Bit Symbol Value Description
27# 1:0 MAP          System memory remap
28#            0x0   Boot Loader Mode. Interrupt vectors are re-mapped to
29#            Boot ROM.
30#            0x1   User RAM Mode. Interrupt vectors are re-mapped to
31#            Static RAM.
32#            0x2   User Flash Mode. Interrupt vectors are not re-mapped
33#            and reside in Flash.
34# 31:2 -     -     Reserved.
35$_TARGETNAME configure -event reset-end {
36	 mww 0x40048000 0x02
37}
38
39# Enable Zephyr thread awareness.
40$_TARGETNAME configure -rtos Zephyr
41
42adapter speed 100
43