1/*
2 * Copyright 2022-2024 NXP
3 * SPDX-License-Identifier: Apache-2.0
4 *
5 */
6
7#include <nxp/nxp_imx/mimx8ml8dvnlz-pinctrl.dtsi>
8
9&pinctrl {
10	uart2_default: uart2_default {
11		group0 {
12			pinmux = <&iomuxc_uart2_rxd_uart_rx_uart2_rx>,
13				<&iomuxc_uart2_txd_uart_tx_uart2_tx>;
14			bias-pull-up;
15			slew-rate = "slow";
16			drive-strength = "x1";
17		};
18	};
19
20	uart4_default: uart4_default {
21		group0 {
22			pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>,
23				<&iomuxc_uart4_txd_uart_tx_uart4_tx>;
24			bias-pull-up;
25			slew-rate = "slow";
26			drive-strength = "x1";
27		};
28	};
29
30	pinmux_mdio: pinmux_mdio {
31		group0 {
32			pinmux = <&iomuxc_sai1_rxd2_enet_mdc_enet1_mdc>,
33				<&iomuxc_sai1_rxd3_enet_mdio_enet1_mdio>;
34			slew-rate = "slow";
35			drive-strength = "x4";
36		};
37	};
38
39	pinmux_enet: pinmux_enet {
40		group0 {
41			pinmux = <&iomuxc_sai1_rxd4_enet_rgmii_rd_enet1_rgmii_rd0>,
42				<&iomuxc_sai1_rxd5_enet_rgmii_rd_enet1_rgmii_rd1>,
43				<&iomuxc_sai1_rxd6_enet_rgmii_rd_enet1_rgmii_rd2>,
44				<&iomuxc_sai1_rxd7_enet_rgmii_rd_enet1_rgmii_rd3>,
45				<&iomuxc_sai1_txc_enet_rgmii_rxc_enet1_rgmii_rxc>,
46				<&iomuxc_sai1_txfs_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>;
47			input-schmitt-enable;
48			slew-rate = "fast";
49			drive-strength = "x1";
50		};
51
52		group1 {
53			pinmux = <&iomuxc_sai1_txd0_enet_rgmii_td_enet1_rgmii_td0>,
54			<&iomuxc_sai1_txd1_enet_rgmii_td_enet1_rgmii_td1>,
55			<&iomuxc_sai1_txd2_enet_rgmii_td_enet1_rgmii_td2>,
56			<&iomuxc_sai1_txd3_enet_rgmii_td_enet1_rgmii_td3>,
57			<&iomuxc_sai1_txd4_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>,
58			<&iomuxc_sai1_txd5_enet_rgmii_txc_enet1_rgmii_txc>;
59			slew-rate = "fast";
60			drive-strength = "x6";
61		};
62
63		group2 {
64			pinmux = <&iomuxc_sai1_rxd0_gpio_io_gpio4_io2>;
65			slew-rate = "fast";
66			drive-strength = "x1";
67		};
68	};
69};
70