1/*
2 * Copyright (c) 2022 Nordic Semiconductor
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	uart0_default: uart0_default {
8		group1 {
9			psels = <NRF_PSEL(UART_TX, 0, 6)>,
10				<NRF_PSEL(UART_RX, 0, 8)>,
11				<NRF_PSEL(UART_RTS, 0, 5)>,
12				<NRF_PSEL(UART_CTS, 0, 7)>;
13		};
14	};
15
16	uart0_sleep: uart0_sleep {
17		group1 {
18			psels = <NRF_PSEL(UART_TX, 0, 6)>,
19				<NRF_PSEL(UART_RX, 0, 8)>,
20				<NRF_PSEL(UART_RTS, 0, 5)>,
21				<NRF_PSEL(UART_CTS, 0, 7)>;
22			low-power-enable;
23		};
24	};
25
26	i2c0_default: i2c0_default {
27		group1 {
28			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
29				<NRF_PSEL(TWIM_SCL, 0, 27)>;
30		};
31	};
32
33	i2c0_sleep: i2c0_sleep {
34		group1 {
35			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
36				<NRF_PSEL(TWIM_SCL, 0, 27)>;
37			low-power-enable;
38		};
39	};
40
41	pwm0_default: pwm0_default {
42		group1 {
43			psels = <NRF_PSEL(PWM_OUT0, 0, 17)>;
44		};
45	};
46
47	pwm0_sleep: pwm0_sleep {
48		group1 {
49			psels = <NRF_PSEL(PWM_OUT0, 0, 17)>;
50			low-power-enable;
51		};
52	};
53
54	spi0_default: spi0_default {
55		group1 {
56			psels = <NRF_PSEL(SPIM_SCK, 0, 25)>,
57				<NRF_PSEL(SPIM_MOSI, 0, 23)>,
58				<NRF_PSEL(SPIM_MISO, 0, 24)>;
59		};
60	};
61
62	spi0_sleep: spi0_sleep {
63		group1 {
64			psels = <NRF_PSEL(SPIM_SCK, 0, 25)>,
65				<NRF_PSEL(SPIM_MOSI, 0, 23)>,
66				<NRF_PSEL(SPIM_MISO, 0, 24)>;
67			low-power-enable;
68		};
69	};
70
71	spi1_default: spi1_default {
72		group1 {
73			psels = <NRF_PSEL(SPIM_SCK, 0, 16)>,
74				<NRF_PSEL(SPIM_MOSI, 0, 20)>,
75				<NRF_PSEL(SPIM_MISO, 0, 14)>;
76		};
77	};
78
79	spi1_sleep: spi1_sleep {
80		group1 {
81			psels = <NRF_PSEL(SPIM_SCK, 0, 16)>,
82				<NRF_PSEL(SPIM_MOSI, 0, 20)>,
83				<NRF_PSEL(SPIM_MISO, 0, 14)>;
84			low-power-enable;
85		};
86	};
87
88};
89