1.. _mps2_an521_board: 2 3ARM MPS2+ AN521 4############### 5 6Overview 7******** 8 9The mps2/an521 board configuration is used by Zephyr applications that run 10on the MPS2+ AN521 board. It provides support for the MPS2+ AN521 ARM Cortex-M33 11CPU and the following devices: 12 13- Nested Vectored Interrupt Controller (NVIC) 14- System Tick System Clock (SYSTICK) 15- Cortex-M System Design Kit GPIO 16- Cortex-M System Design Kit UART 17 18.. image:: img/mps2_an521.jpg 19 :align: center 20 :alt: ARM MPS2+ AN521 21 22In addition to enabling actual hardware usage, this board configuration can 23also use QEMU to emulate the AN521 platform running on the MPS2+. 24 25More information about the board can be found at the `MPS2 FPGA Website`_. 26 27.. note:: 28 This board configuration makes no claims about its suitability for use 29 with actual MPS2 hardware systems using AN521, or any other hardware 30 system. It has been tested on actual hardware, but its primary purpose is 31 for use with QEMU and unit tests for the ARM Cortex-M33. 32 33 34Zephyr board options 35==================== 36 37The MPS2+ AN521 is a dual core SoC with Cortex-M33 architecture on both cores 38(CPU0 and CPU1). Zephyr provides support for building firmware 39images for both CPU0 and CPU1. For CPU0 supporting ARM Security Extensions 40both Secure and Non-Secure firmware images may be built. 41 42The BOARD options are summarized below: 43 44+----------------------+-------------------------------------------------------+ 45| BOARD | Description | 46+======================+=======================================================+ 47| mps2/an521/cpu0 | For building Secure (or Secure-only) firmware on CPU0 | 48+----------------------+-------------------------------------------------------+ 49| mps2/an521/cpu0/ns | For building Non-Secure firmware for CPU0 | 50+----------------------+-------------------------------------------------------+ 51| mps2/an521/cpu1 | For building firmware on CPU1 | 52+----------------------+-------------------------------------------------------+ 53 54Memory Partitioning 55=================== 56 57The AN521 has 4MB allocated for code space, and 4MB for SRAM. These memory 58regions are shared across both cores, and are aliased in both secure and 59non-secure regions, where the secure memory alias has an offset of 600x10000000 relative to non-secure. 61 62The following memory map and partitioning schemes are used by default, where 63the offset value is the offset from the base of the 4MB code or SRAM block, 64ignoring the S/NS alias difference. 65 66+-------------------------+-----+----------------+----------------+------------+ 67| Board | CPU | Code (Offset) | SRAM (Offset) | S/NS Alias | 68+=========================+=====+================+================+============+ 69| mps2/an521/cpu0 | 0 | 4MB (0) | 4MB (0) | S | 70+-------------------------+-----+----------------+----------------+------------+ 71| mps2/an521/cpu0/ns | 0 | 512KB (1MB) | 512KB (1MB) | NS | 72+-------------------------+-----+----------------+----------------+------------+ 73| mps2/an521/cpu1 | 1 | 468KB (3628KB) | 512KB (1.5MB) | NS | 74+-------------------------+-----+----------------+----------------+------------+ 75 76The ``mps2/an521/cpu0/ns`` board target is intended to be used with TF-M, with the 77Zephyr memory map matching the AN521 memory map defined upstream in TF-M. TF-M 78boots the secure processing environment before initialising Zephyr in the 79non-secure processing environment. The non-secure Zephyr image is offset to 80make room for the secure bootloader, and the secure firmware (TF-M), resulting 81in a starting address of 0x00100000. SRAM begins with a 1MB offset at 820x28100000. 83 84The ``mps2/an521/cpu1`` board target is setup for the second core on the 85AN521, using the final 468KB code memory in the 4MB code block. This value 86is chosen to maintain compatibility with TF-M, which marks that final 468KB 87code region as ``Unused``. Code memory thus starts with an offset of 883628KB (address 0x0038B000), and sram starts with an offset of 1.5MB 89(address 0x28180000). 90 91This memory map enables the two alternative board targets to be used together 92if required, at the cost of reducing the amount of code memory available on 93the second core to the worst-case scenario from TF-M. 94 95When using one of the alternative board targets (``mps2/an521/cpu0/ns`` or 96``mps2/an521/cpu1``), care needs to be taken with the amount of code or 97SRAM memory used on the primary board target (``mps2/an521``) since there is 98some overlap in the memory maps. 99 100Hardware 101******** 102 103ARM MPS2+ AN521 provides the following hardware components: 104 105- Dual core ARM Cortex-M33 106- Soft Macro Model (SMM) implementation of SSE-200 subsystem 107- Memory 108 109 - 4MB of code memory (SSRAM1) 110 - 4MB of SRAM (SSRAM2 and SSRAM3) 111 - 16MB of parallel SRAM (PSRAM, non-secure only) 112 - 8KB of NVM code 113 114- Debug 115 116 - P-JTAG, SWD & 16-bit TRACE 117 - UART port 118 119- Interface 120 121 - AHB GPIO connected to the EXP port 122 - UART 123 - SPI 124 - I2C 125 - I2S 126 - Color LCD serial interface 127 - Ethernet 128 - VGA 129 130- On-board Peripherals 131 132 - Color LCD 133 - 8 LEDs 134 - 8 Switches 135 - External SSRAM1, SSRAM2 & SSRAM3 136 - SMSC9220 137 - CS42L52 138 139 140User push buttons 141================= 142 143The mps2/an521 board provides the following user push buttons: 144 145- ON power on 146- nSRST: Cortex-M33 system reset and CoreSight debug reset 147- USERPB0 and USERPB1: User defined buttons 148 149 150Supported Features 151=================== 152 153The mps2/an521 board configuration supports the following hardware features: 154 155+-----------+------------+-------------------------------------+ 156| Interface | Controller | Driver/Component | 157+===========+============+=====================================+ 158| NVIC | on-chip | nested vector interrupt controller | 159+-----------+------------+-------------------------------------+ 160| SYSTICK | on-chip | systick | 161+-----------+------------+-------------------------------------+ 162| UART | on-chip | serial port-polling; | 163| | | serial port-interrupt | 164+-----------+------------+-------------------------------------+ 165| PINMUX | on-chip | pinmux | 166+-----------+------------+-------------------------------------+ 167| GPIO | on-chip | gpio | 168+-----------+------------+-------------------------------------+ 169| WATCHDOG | on-chip | watchdog | 170+-----------+------------+-------------------------------------+ 171| TIMER | on-chip | timer | 172+-----------+------------+-------------------------------------+ 173 174Other hardware features are not currently supported by the port. 175See the `MPS2 FPGA Website`_ for a complete list of MPS2+ AN521 board hardware 176features. 177 178The default configuration can be found in 179:zephyr_file:`boards/arm/mps2/mps2_an521_cpu0_defconfig`. 180 181Interrupt Controller 182==================== 183 184MPS2+ AN521 is a Cortex-M33 based SoC and has 15 fixed exceptions and 77 IRQs. 185 186A Cortex-M33-based board uses vectored exceptions. This means each exception 187calls a handler directly from the vector table. 188 189Zephyr provides handlers for exceptions 1-7, 11, 12, 14, and 15, as listed 190in the following table: 191 192+------+------------+----------------+--------------------------+ 193| Exc# | Name | Remarks | Used by Zephyr Kernel | 194+======+============+================+==========================+ 195| 1 | Reset | | system initialization | 196+------+------------+----------------+--------------------------+ 197| 2 | NMI | | system fatal error | 198+------+------------+----------------+--------------------------+ 199| 3 | Hard fault | | system fatal error | 200+------+------------+----------------+--------------------------+ 201| 4 | MemManage | MPU fault | system fatal error | 202+------+------------+----------------+--------------------------+ 203| 5 | Bus | | system fatal error | 204+------+------------+----------------+--------------------------+ 205| 6 | Usage | Undefined | system fatal error | 206| | fault | instruction, | | 207| | | or switch | | 208| | | attempt to ARM | | 209| | | mode | | 210+------+------------+----------------+--------------------------+ 211| 7 | SecureFault| Unauthorized | system fatal error | 212| | | access to | | 213| | | secure region | | 214| | | from ns space | | 215+------+------------+----------------+--------------------------+ 216| 8 | Reserved | | not handled | 217+------+------------+----------------+--------------------------+ 218| 9 | Reserved | | not handled | 219+------+------------+----------------+--------------------------+ 220| 10 | Reserved | | not handled | 221+------+------------+----------------+--------------------------+ 222| 11 | SVC | | system calls, kernel | 223| | | | run-time exceptions, | 224| | | | and IRQ offloading | 225+------+------------+----------------+--------------------------+ 226| 12 | Debug | | system fatal error | 227| | monitor | | | 228+------+------------+----------------+--------------------------+ 229| 13 | Reserved | | not handled | 230+------+------------+----------------+--------------------------+ 231| 14 | PendSV | | context switch | 232+------+------------+----------------+--------------------------+ 233| 15 | SYSTICK | | system clock | 234+------+------------+----------------+--------------------------+ 235| 16 | Reserved | | not handled | 236+------+------------+----------------+--------------------------+ 237| 17 | Reserved | | not handled | 238+------+------------+----------------+--------------------------+ 239| 18 | Reserved | | not handled | 240+------+------------+----------------+--------------------------+ 241 242Pin Mapping 243=========== 244 245The ARM MPS2+ AN521 Board has 4 CMSDK AHB GPIO controllers. Each providing 16 246bits of IO. These controllers are responsible for pin-muxing, input/output, 247pull-up, etc. 248 249All GPIO controller pins are exposed via the following sequence of pin numbers: 250 251- Pins 0 - 15 are for GPIO0 252- Pins 16 - 31 are for GPIO1 253- Pins 32 - 47 are for GPIO2 254- Pins 48 - 51 are for GPIO3 255 256Mapping from the ARM MPS2+ AN521 Board pins to GPIO controllers: 257 258.. rst-class:: rst-columns 259 260 - D0 : EXT_0 261 - D1 : EXT_4 262 - D2 : EXT_2 263 - D3 : EXT_3 264 - D4 : EXT_1 265 - D5 : EXT_6 266 - D6 : EXT_7 267 - D7 : EXT_8 268 - D8 : EXT_9 269 - D9 : EXT_10 270 - D10 : EXT_12 271 - D11 : EXT_13 272 - D12 : EXT_14 273 - D13 : EXT_11 274 - D14 : EXT_15 275 - D15 : EXT_5 276 - D16 : EXT_16 277 - D17 : EXT_17 278 - D18 : EXT_18 279 - D19 : EXT_19 280 - D20 : EXT_20 281 - D21 : EXT_21 282 - D22 : EXT_22 283 - D23 : EXT_23 284 - D24 : EXT_24 285 - D25 : EXT_25 286 - D26 : EXT_26 287 - D27 : EXT_30 288 - D28 : EXT_28 289 - D29 : EXT_29 290 - D30 : EXT_27 291 - D31 : EXT_32 292 - D32 : EXT_33 293 - D33 : EXT_34 294 - D34 : EXT_35 295 - D35 : EXT_36 296 - D36 : EXT_38 297 - D37 : EXT_39 298 - D38 : EXT_40 299 - D39 : EXT_44 300 - D40 : EXT_41 301 - D41 : EXT_31 302 - D42 : EXT_37 303 - D43 : EXT_42 304 - D44 : EXT_43 305 - D45 : EXT_45 306 - D46 : EXT_46 307 - D47 : EXT_47 308 - D48 : EXT_48 309 - D49 : EXT_49 310 - D50 : EXT_50 311 - D51 : EXT_51 312 313Peripheral Mapping: 314 315.. rst-class:: rst-columns 316 317 - UART_3_RX : D0 318 - UART_3_TX : D1 319 - SPI_3_CS : D10 320 - SPI_3_MOSI : D11 321 - SPI_3_MISO : D12 322 - SPI_3_SCLK : D13 323 - I2C_3_SDA : D14 324 - I2C_3_SCL : D15 325 - UART_4_RX : D26 326 - UART_4_TX : D30 327 - SPI_4_CS : D36 328 - SPI_4_MOSI : D37 329 - SPI_4_MISO : D38 330 - SPI_4_SCK : D39 331 - I2C_4_SDA : D40 332 - I2C_4_SCL : D41 333 334For more details refer to `MPS2+ AN521 Technical Reference Manual (TRM)`_. 335 336LED 337============ 338 339MPS2+ has 8 built-in LEDs connected to Serial Configuration Controller (SCC). 340 341.. note:: The SCC register CFG_REG1 Bits [7:0] for LEDa, 0 = OFF 1 = ON. 342 343System Clock 344============ 345 346MPS2+ AN521 has several clocks connected: 347 348.. rst-class:: rst-columns 349 350 - MAINCLK : 20MHz 351 - SYSCLK : 20MHz 352 - S32KCLK : 32kHz 353 - TRACECLK : 20MHz 354 - SWCLKTCK : 20MHz 355 - TRACECLKIN : 20MHz 356 357Serial Port 358=========== 359 360The MPS2+ AN521 has five UARTs. The Zephyr console output by default, uses 361UART0, which is J10 on the board. 362 363UART2 is reserved. And UART 1, 3 and 4 are alt-functions on the EXP ports. 364 365Security components 366=================== 367 368- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is used to define 369 secure and non-secure memory maps. By default, all of the memory space is 370 defined to be secure accessible only 371- Secure and Non-secure peripherals via the Peripheral Protection Controller 372 (PPC). Peripherals can be assigned as secure or non-secure accessible 373- Secure boot 374- Secure `AMBA®`_ interconnect 375 376Serial Configuration Controller (SCC) 377===================================== 378 379The MPS2+ AN521 implements a Serial Configuration Control (SCC) register. 380The purpose of this register is to allow individual control of clocks, 381reset-signals and interrupts to peripherals, and pin-muxing, and the LEDs and 382switches. 383 384Programming and Debugging 385************************* 386 387MPS2+ AN521 (CPU0) supports the Armv8m Security Extension. 388Applications built for the mps2/an521 board by default 389boot in the Secure state. 390 391MPS2+ AN521 (CPU1) does not support the Armv8m Security Extension. 392 393Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| 394============================================================================= 395 396Applications on the MPS2+ AN521 (CPU0) may contain a Secure and a Non-Secure 397firmware image. The Secure image can be built using either Zephyr 398or `Trusted Firmware M`_ (TF-M). Non-Secure firmware images are always built 399using Zephyr. The two alternatives are described below. 400 401.. note:: 402 403 By default the Secure image for the MPS2+ AN521 (CPU0) is built 404 using TF-M. 405 406Building the Secure firmware with TF-M 407-------------------------------------- 408 409The process to build the Secure firmware image using TF-M and the Non-Secure 410firmware image using Zephyr requires the following steps: 411 4121. Build the Non-Secure Zephyr application 413 for MPS2+ AN521 (CPU0) using ``-DBOARD=mps2/an521/cpu0/ns``. 414 To invoke the building of TF-M the Zephyr build system requires the 415 Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by 416 default when building Zephyr as a Non-Secure application. 417 The Zephyr build system will perform the following steps automatically: 418 419 * Build the Non-Secure firmware image as a regular Zephyr application 420 * Build a TF-M (secure) firmware image 421 * Merge the output image binaries together 422 * Optionally build a bootloader image (MCUboot) 423 424.. note:: 425 426 Depending on the TF-M configuration, an application DTS overlay may be 427 required, to adjust the Non-Secure image Flash and SRAM starting address 428 and sizes. 429 430Building the Secure firmware using Zephyr 431----------------------------------------- 432 433The process to build the Secure and the Non-Secure firmware images 434using Zephyr requires the following steps: 435 4361. Build the Secure Zephyr application for MPS2+ AN521 (CPU0) 437 using ``-DBOARD=mps2/an521`` and 438 ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` 439 in the application project configuration file. 4402. Build the Non-Secure Zephyr application for MPS2+ AN521 (CPU0) 441 using ``-DBOARD=mps2/an521/cpu0/ns``. 4423. Merge the two binaries together. 443 444Building a Secure only application on MPS2+ AN521 (CPU0) 445======================================================== 446 447Build the Zephyr app in the usual way (see :ref:`build_an_application` 448and :ref:`application_run`), using ``-DBOARD=mps2/an521`` for 449the firmware running on the MPS2+ AN521 (CPU0). 450 451When building a Secure/Non-Secure application for the MPS2+ AN521 (CPU0), 452the Secure application will have to set the SAU/IDAU configuration to allow 453Non-Secure access to all CPU resources utilized by the Non-Secure application 454firmware. SAU/IDAU configuration shall take place before jumping to the 455Non-Secure application. 456 457The following system components are required to be properly configured during the 458secure firmware: 459 460- AHB5 TrustZone Memory Protection Controller (MPC) 461- AHB5 TrustZone Peripheral Protection Controller (PPC) 462- Implementation-Defined Attribution Unit (IDAU) 463 464For more details refer to `Corelink SSE-200 Subsystem`_. 465 466 467 468Building standalone applications on MPS2+ AN521 CPU1 469==================================================== 470 471Applications may be built for the second Cortex-M33 472(remote) core of MPS2+ AN521. The core is referred to as CPU1. 473 474Build the Zephyr app in the usual way (see :ref:`build_an_application` 475and :ref:`application_run`), using ``-DBOARD=mps2/an521/cpu1`` for 476the firmware running on the MPS2+ AN521 (CPU1). 477 478The Zephyr build will automatically trigger building a minimal (empty) 479secure-only firmware for CPU0, which will be used to boot the remote 480core (CPU1). 481 482 483Flashing 484======== 485 486MPS2+ AN521 provides: 487 488- A USB connection to the host computer, which exposes a Mass Storage 489- A Serial Port which is J10 on MPS2+ board 490 491Build applications as described above. 492Here is an example for the :ref:`hello_world` application built as 493a secure-only application for CPU0. 494 495.. zephyr-app-commands:: 496 :zephyr-app: samples/hello_world 497 :board: mps2/an521 498 :goals: build 499 500 501Open a serial terminal (minicom, putty, etc.) with the following settings: 502 503- Speed: 115200 504- Data: 8 bits 505- Parity: None 506- Stop bits: 1 507 508Reset the board, and you should see the following message on the corresponding 509serial port: 510 511.. code-block:: console 512 513 Hello World! mps2_an521 514 515 516Uploading an application to MPS2+ AN521 517--------------------------------------- 518 519Applications can be in elf, hex or bin format. The binaries are flashed when 520the board boots up, using files stored on the on-board Micro SD card. The 521Motherboard Configuration Controller (MCC) is responsible for loading the FPGA 522image and binaries. 523 524Connect the MPS2+ to your host computer using the USB port. You should see a 525USB connection exposing a Mass Storage (``V2M_MPS2`` by default). 526 527The update requires 3 steps: 528 5291. Copy application files to ``<MPS2 device name>/SOFTWARE/``. 5302. Open ``<MPS2 device name>/MB/HBI0263C/AN521/images.txt``. 5313. Update the ``AN521/images.txt`` file as follows: 532 533.. code-block:: bash 534 535 TITLE: Versatile Express Images Configuration File 536 537 [IMAGES] 538 TOTALIMAGES: 1 ;Number of Images (Max: 32) 539 540 IMAGE0ADDRESS: 0x10000000 ;Please select the required executable program 541 542 IMAGE0FILE: \SOFTWARE\zephyr.bin 543 544 545Reset the board, and you should see the following message on the corresponding 546serial port: 547 548.. code-block:: console 549 550 Hello World! mps2_an521 551 552.. note:: Refer to the tfm_integration sample for more details about integrating with TF-M and multiple images scenario. 553 554 555.. _MPS2 FPGA Website: 556 https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps2 557 558.. _MPS2+ AN521 Technical Reference Manual (TRM): 559 https://developer.arm.com/documentation/dai0521/latest/ 560 561.. _Cortex M33 Generic User Guide: 562 https://developer.arm.com/documentation/100235/latest/ 563 564.. _Trusted Firmware M: 565 https://tf-m-user-guide.trustedfirmware.org/building/tfm_build_instruction.html 566 567.. _Corelink SSE-200 Subsystem: 568 https://developer.arm.com/documentation/dto0051/latest/subsystem-overview/about-the-sse-200 569 570.. _IDAU: 571 https://developer.arm.com/documentation/100690/latest/Attribution-units--SAU-and-IDAU- 572 573.. _AMBA®: 574 https://developer.arm.com/products/architecture/system-architectures/amba 575
