1.. _mps2_an385_board:
2
3ARM V2M MPS2
4############
5
6Overview
7********
8
9The mps2/an385 board configuration is used by Zephyr applications that run on
10the V2M MPS2 board. It provides support for the ARM Cortex-M3 (AN385) CPU and
11the following devices:
12
13- Nested Vectored Interrupt Controller (NVIC)
14- System Tick System Clock (SYSTICK)
15- Cortex-M System Design Kit UART
16
17.. image:: img/mps2_an385.jpg
18     :align: center
19     :alt: ARM V2M MPS2
20
21In addition to enabling actual hardware usage, this board configuration can
22also use QEMU to emulate the AN385 platform running on the MPS2+.
23
24More information about the board can be found at the `V2M MPS2 Website`_.
25
26The Application Note AN385 can be found at `Application Note AN385`_.
27
28.. note::
29   This board configuration makes no claims about its suitability for use
30   with actual MPS2 hardware systems using AN385, or any other hardware
31   system. It has been tested on actual hardware, but its primary purpose is
32   for use with QEMU and unit tests.
33
34Hardware
35********
36
37ARM V2M MPS2 provides the following hardware components:
38
39- ARM Cortex-M3 (AN385)
40- ARM IoT Subsystem for Cortex-M
41- Form factor: 140x120cm
42- ZBTSRAM: 8MB single cycle SRAM, 16MB PSRAM
43- Video: QSVGA touch screen panel, 4bit RGB VGA connector
44- Audio: Audio Codec
45- Debug:
46
47  - ARM JTAG20 connector
48  - ARM parallel trace connector (MICTOR38)
49  - 20 pin Cortex debug connector
50  - 10 pin Cortex debug connector
51  - ILA connector for FPGA debug
52
53- Expansion
54
55  - GPIO
56  - SPI
57
58.. note::
59   4 MB of flash memory (in ZBTSRAM 1, starting at address 0x00400000) and 4 MB of RAM
60   (in ZBTSRAM 2 & 3, starting at address 0x20000000) are available.
61
62Supported Features
63==================
64
65The mps2/an385 board configuration supports the following hardware features:
66
67+-----------+------------+-------------------------------------+
68| Interface | Controller | Driver/Component                    |
69+===========+============+=====================================+
70| NVIC      | on-chip    | nested vector interrupt controller  |
71+-----------+------------+-------------------------------------+
72| SYSTICK   | on-chip    | systick                             |
73+-----------+------------+-------------------------------------+
74| UART      | on-chip    | serial port-polling;                |
75|           |            | serial port-interrupt               |
76+-----------+------------+-------------------------------------+
77| GPIO      | on-chip    | gpio                                |
78+-----------+------------+-------------------------------------+
79| WATCHDOG  | on-chip    | watchdog                            |
80+-----------+------------+-------------------------------------+
81| TIMER     | on-chip    | counter                             |
82+-----------+------------+-------------------------------------+
83| DUALTIMER | on-chip    | counter                             |
84+-----------+------------+-------------------------------------+
85
86Other hardware features are not currently supported by the port.
87See the `V2M MPS2 Website`_ for a complete list of V2M MPS2 board hardware
88features.
89
90The default configuration can be found in
91:zephyr_file:`boards/arm/mps2/mps2_an385_defconfig`
92
93Interrupt Controller
94====================
95
96MPS2 is a Cortex-M3 based SoC and has 15 fixed exceptions and 45 IRQs.
97
98A Cortex-M3/4-based board uses vectored exceptions. This means each exception
99calls a handler directly from the vector table.
100
101Handlers are provided for exceptions 1-6, 11-12, and 14-15. The table here
102identifies the handlers used for each exception.
103
104+------+------------+----------------+--------------------------+
105| Exc# | Name       | Remarks        | Used by Zephyr Kernel    |
106+======+============+================+==========================+
107| 1    | Reset      |                | system initialization    |
108+------+------------+----------------+--------------------------+
109| 2    | NMI        |                | system fatal error       |
110+------+------------+----------------+--------------------------+
111| 3    | Hard fault |                | system fatal error       |
112+------+------------+----------------+--------------------------+
113| 4    | MemManage  | MPU fault      | system fatal error       |
114+------+------------+----------------+--------------------------+
115| 5    | Bus        |                | system fatal error       |
116+------+------------+----------------+--------------------------+
117| 6    | Usage      | undefined      | system fatal error       |
118|      | fault      | instruction,   |                          |
119|      |            | or switch      |                          |
120|      |            | attempt to ARM |                          |
121|      |            | mode           |                          |
122+------+------------+----------------+--------------------------+
123| 11   | SVC        |                | system calls, kernel     |
124|      |            |                | run-time exceptions,     |
125|      |            |                | and IRQ offloading       |
126+------+------------+----------------+--------------------------+
127| 12   | Debug      |                | system fatal error       |
128|      | monitor    |                |                          |
129+------+------------+----------------+--------------------------+
130| 14   | PendSV     |                | context switch           |
131+------+------------+----------------+--------------------------+
132| 15   | SYSTICK    |                | system clock             |
133+------+------------+----------------+--------------------------+
134
135Pin Mapping
136===========
137
138The ARM V2M MPS2 Board has 4 GPIO controllers. These controllers are responsible
139for pin muxing, input/output, pull-up, etc.
140
141All GPIO controller pins are exposed via the following sequence of pin numbers:
142
143- Pins 0 - 15 are for GPIO 0
144- Pins 16 - 31 are for GPIO 1
145- Pins 32 -  47 are for GPIO 2
146- Pins 48 -  51 are for GPIO 3
147
148Mapping from the ARM MPS2 Board pins to GPIO controllers:
149
150.. rst-class:: rst-columns
151
152   - D0 : EXT_0
153   - D1 : EXT_4
154   - D2 : EXT_2
155   - D3 : EXT_3
156   - D4 : EXT_1
157   - D5 : EXT_6
158   - D6 : EXT_7
159   - D7 : EXT_8
160   - D8 : EXT_9
161   - D9 : EXT_10
162   - D10 : EXT_12
163   - D11 : EXT_13
164   - D12 : EXT_14
165   - D13 : EXT_11
166   - D14 : EXT_15
167   - D15 : EXT_5
168   - D16 : EXT_16
169   - D17 : EXT_17
170   - D18 : EXT_18
171   - D19 : EXT_19
172   - D20 : EXT_20
173   - D21 : EXT_21
174   - D22 : EXT_22
175   - D23 : EXT_23
176   - D24 : EXT_24
177   - D25 : EXT_25
178   - D26 : EXT_26
179   - D27 : EXT_30
180   - D28 : EXT_28
181   - D29 : EXT_29
182   - D30 : EXT_27
183   - D31 : EXT_32
184   - D32 : EXT_33
185   - D33 : EXT_34
186   - D34 : EXT_35
187   - D35 : EXT_36
188   - D36 : EXT_38
189   - D37 : EXT_39
190   - D38 : EXT_40
191   - D39 : EXT_44
192   - D40 : EXT_41
193   - D41 : EXT_31
194   - D42 : EXT_37
195   - D43 : EXT_42
196   - D44 : EXT_43
197   - D45 : EXT_45
198   - D46 : EXT_46
199   - D47 : EXT_47
200   - D48 : EXT_48
201   - D49 : EXT_49
202   - D50 : EXT_50
203   - D51 : EXT_51
204
205Peripheral Mapping:
206
207.. rst-class:: rst-columns
208
209   - UART_3_RX : D0
210   - UART_3_TX : D1
211   - SPI_3_CS : D10
212   - SPI_3_MOSI : D11
213   - SPI_3_MISO : D12
214   - SPI_3_SCLK : D13
215   - I2C_3_SDA : D14
216   - I2C_3_SCL : D15
217   - UART_4_RX : D26
218   - UART_4_TX : D30
219   - SPI_4_CS : D36
220   - SPI_4_MOSI : D37
221   - SPI_4_MISO : D38
222   - SPI_4_SCK : D39
223   - I2C_4_SDA : D40
224   - I2C_4_SCL : D41
225
226For more details please refer to `MPS2 Technical Reference Manual (TRM)`_.
227
228System Clock
229============
230
231The V2M MPS2 main clock is 24 MHz.
232
233Serial Port
234===========
235
236The V2M MPS2 processor has five UARTs. Both the UARTs have only two wires for
237RX/TX and no flow control (CTS/RTS) or FIFO. The Zephyr console output, by
238default, is utilizing UART0.
239
240Programming and Debugging
241*************************
242
243Flashing
244========
245
246V2M MPS2 provides:
247
248- A USB connection to the host computer, which exposes a Mass Storage and an
249  USB Serial Port.
250- A Serial Flash device, which implements the USB flash disk file storage.
251- A physical UART connection which is relayed over interface USB Serial port.
252
253Flashing an application to V2M MPS2
254-----------------------------------
255
256Here is an example for the :ref:`hello_world` application.
257
258.. zephyr-app-commands::
259   :zephyr-app: samples/hello_world
260   :board: mps2/an385
261   :goals: build
262
263Connect the V2M MPS2 to your host computer using the USB port and you should
264see a USB connection which exposes a Mass Storage and a USB Serial Port.
265Copy the generated zephyr.bin in the exposed drive.
266Reset the board and you should be able to see on the corresponding Serial Port
267the following message:
268
269.. code-block:: console
270
271   Hello World! arm
272
273
274.. _V2M MPS2 Website:
275   https://developer.mbed.org/platforms/ARM-MPS2/
276
277.. _MPS2 Technical Reference Manual (TRM):
278   http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_05_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_05_en.pdf
279
280.. _Application Note AN385:
281   http://infocenter.arm.com/help/topic/com.arm.doc.dai0385c/DAI0385C_cortex_m3_on_v2m_mps2.pdf
282