1.. _96b_avenger96: 2 396Boards Avenger96 4################## 5 6Overview 7******** 8 996Boards Avenger96 board is based on ST Microelectronics STM32MP157A 10multi-core processor, composed of a dual Cortex®-A7 and a single Cortex®-M4 11core. Zephyr OS is ported to run on the Cortex®-M4 core. 12 13- Board features: 14 15 - PMIC: STPMIC1A 16 - RAM: 1024 Mbyte @ 533MHz 17 - Storage: 18 19 - eMMC: v4.51: 8 Gbyte 20 - QSPI: 2Mbyte 21 - EEPROM: 128 byte 22 - microSD Socket: UHS-1 v3.01 23 - Ethernet: 10/100/1000 Mbit/s, IEEE 802.3 Compliant 24 - Wireless: 25 26 - WiFi: 5 GHz & 2.4GHz IEEE 802.11a/b/g/n/ac 27 - Bluetooth: v4.2 (BR/EDR/BLE) 28 - USB: 29 30 - Host - 2x type A, 2.0 high-speed 31 - OTG: - 1x type micro-AB, 2.0 high-speed 32 - HDMI: WXGA (1366x768)@ 60 fps, HDMI 1.4 33 - Connectors: 34 35 - 40-Pin Low Speed Header 36 - 60-Pin High Speed Header 37 - LEDs: 38 39 - 4x Green user LEDs 40 - 1x Blue Bluetooth LED 41 - 1x Yellow WiFi LED 42 - 1x Red power supply LED 43 44.. image:: img/96b_avenger96.jpg 45 :align: center 46 :alt: 96Boards Avenger96 47 48More information about the board can be found at the 49`96Boards website`_. 50 51Hardware 52******** 53 54The STM32MP157A SoC provides the following hardware capabilities: 55 56- Core: 57 58 - 32-bit dual-core Arm® Cortex®-A7 59 60 - L1 32-Kbyte I / 32-Kbyte D for each core 61 - 256-Kbyte unified level 2 cache 62 - Arm® NEON™ 63 64 - 32-bit Arm® Cortex®-M4 with FPU/MPU 65 66 - Up to 209 MHz (Up to 703 CoreMark®) 67 68- Memories: 69 70 - External DDR memory up to 1 Gbyte. 71 - 708 Kbytes of internal SRAM: 256 KB of AXI SYSRAM + 384 KB of AHB SRAM + 72 64 KB of AHB SRAM in backup domain. 73 - Dual mode Quad-SPI memory interface 74 - Flexible external memory controller with up to 16-bit data bus 75 76- Clock management: 77 78 - Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz 79 LSI oscillator 80 - External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator 81 - 6 × PLLs with fractional mode 82 83- General-purpose input/outputs: 84 85 - Up to 176 I/O ports with interrupt capability 86 87- Interconnect matrix 88 89- 3 DMA controllers 90 91- Communication peripherals: 92 93 - 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus) 94 - 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave) 95 - 6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy) 96 - 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx) 97 - SPDIF Rx with 4 inputs 98 - HDMI-CEC interface 99 - MDIO Slave interface 100 - 3 × SDMMC up to 8-bit (SD / e•MMC™ / SDIO) 101 - 2 × CAN controllers supporting CAN FD protocol, TTCAN capability 102 - 2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously 103 - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI) 104 - 8- to 14-bit camera interface up to 140 Mbyte/s 105 - 6 analog peripherals 106 - 2 × ADCs with 16-bit max. resolution. 107 - 1 × temperature sensor 108 - 2 × 12-bit D/A converters (1 MHz) 109 - 1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6 110 filters 111 - Internal or external ADC/DAC reference VREF+ 112 113- Graphics: 114 115 - 3D GPU: Vivante® - OpenGL® ES 2.0 116 - LCD-TFT controller, up to 24-bit // RGB888, up to WXGA (1366 × 768) @60 fps 117 - MIPI® DSI 2 data lanes up to 1 GHz each 118 119- Timers: 120 121 - 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature 122 (incremental) encoder input 123 - 2 × 16-bit advanced motor control timers 124 - 10 × 16-bit general-purpose timers (including 2 basic timers without PWM) 125 - 5 × 16-bit low-power timers 126 - RTC with sub-second accuracy and hardware calendar 127 - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor) 128 - 1 × SysTick Cortex®-M4 timer 129 130- Hardware acceleration: 131 132 - HASH (MD5, SHA-1, SHA224, SHA256), HMAC 133 - 2 × true random number generator (3 oscillators each) 134 - 2 × CRC calculation unit 135 136- Debug mode: 137 138 - Arm® CoreSight™ trace and debug: SWD and JTAG interfaces 139 - 8-Kbyte embedded trace buffer 140 - 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user 141 142More information about STM32P157A can be found here: 143 144- `STM32MP157A on www.st.com`_ 145- `STM32MP157A reference manual`_ 146 147Supported Features 148================== 149 150The Zephyr 96b_avenger96 board configuration supports the following hardware 151features: 152 153+-----------+------------+-------------------------------------+ 154| Interface | Controller | Driver/Component | 155+===========+============+=====================================+ 156| NVIC | on-chip | nested vector interrupt controller | 157+-----------+------------+-------------------------------------+ 158| GPIO | on-chip | gpio | 159+-----------+------------+-------------------------------------+ 160| UART | on-chip | serial port-polling; | 161| | | serial port-interrupt | 162+-----------+------------+-------------------------------------+ 163| PINMUX | on-chip | pinmux | 164+-----------+------------+-------------------------------------+ 165 166The default configuration can be found in 167:zephyr_file:`boards/96boards/avenger96/96b_avenger96_defconfig` 168 169 170Connections and IOs 171=================== 172 17396Boards Avenger96 Board schematic is available here: 174`Avenger96 board schematics`_. 175 176 177Default Zephyr Peripheral Mapping: 178---------------------------------- 179 180- UART_7 TX/RX/RTS/CTS : PE8/PE7/PE9/PE10 (UART console) 181- UART_4 TX/RX : PD1/PB2 182 183System Clock 184------------ 185 186The Cortex®-M4 Core is configured to run at a 209 MHz clock speed. This value 187must match the configured mlhclk_ck frequency. 188 189Serial Port 190----------- 191 19296Boards Avenger96 board has 3 U(S)ARTs. The Zephyr console output is assigned 193by default to the RAM console to be dumped by the Linux Remoteproc Framework 194on Cortex®-A7 core. Alternatively, Zephyr console output can be assigned to 195UART7 which is disabled by default. UART console can be enabled through 196board's devicetree and 96b_avenger96_defconfig board file (or prj.conf 197project files), and will disable existing RAM console output. Default UART 198console settings are 115200 8N1. 199 200Programming and Debugging 201************************* 202 203The STM32MP157A doesn't have QSPI flash for the Cortex®-M4 and it needs to be 204started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the 205Cortex®-M4 binary application into the RAM, and get the Cortex®-M4 out of reset. 206The Cortex®-A7 can perform these steps at bootloader level or after the Linux 207system has booted. 208 209The Cortex®-M4 can use up to 2 different RAMs. The program pointer starts at 210address 0x00000000 (RETRAM), the vector table should be loaded at this address 211These are the memory mappings for Cortex®-A7 and Cortex®-M4: 212 213+------------+-----------------------+------------------------+----------------+ 214| Region | Cortex®-A7 | Cortex®-M4 | Size | 215+============+=======================+========================+================+ 216| RETRAM | 0x38000000-0x3800FFFF | 0x00000000-0x0000FFFF | 64KB | 217+------------+-----------------------+------------------------+----------------+ 218| MCUSRAM | 0x10000000-0x1005FFFF | 0x10000000-0x1005FFFF | 384KB | 219+------------+-----------------------+------------------------+----------------+ 220| DDR | 0xC0000000-0xFFFFFFFF | | up to 1 GB | 221+------------+-----------------------+------------------------+----------------+ 222 223 224Refer to `stm32mp157 boot Cortex-M4 firmware`_ wiki page for instruction 225to load and start the Cortex-M4 firmware. 226 227Debugging 228========= 229 230You can debug an application using OpenOCD and GDB. The Solution proposed below 231is based on the Linux STM32MP1 SDK OpenOCD and is available only for a Linux 232environment. The firmware must first be loaded by the Cortex®-A7. Developer 233then attaches the debugger to the running Zephyr using OpenOCD. 234 235Prerequisite 236------------ 237install `stm32mp1 developer package`_. 238 2391) start OpenOCD in a dedicated terminal 240 241 - Start up the sdk environment:: 242 243 source <SDK installation directory>/environment-setup-cortexa7hf-neon-vfpv4-openstlinux_weston-linux-gnueabi 244 245 - Start OpenOCD:: 246 247 ${OECORE_NATIVE_SYSROOT}/usr/bin/openocd -s ${OECORE_NATIVE_SYSROOT}/usr/share/openocd/scripts -f board/stm32mp15x_ev1_jlink_jtag.cfg 248 2492) run gdb in Zephyr environment 250 251 .. code-block:: console 252 253 # On Linux 254 cd $ZEPHYR_BASE/samples/hello_world 255 mkdir -p build && cd build 256 257 # Use cmake to configure a Ninja-based build system: 258 cmake -GNinja -DBOARD=96b_avenger96 .. 259 260 # Now run ninja on the generated build system: 261 ninja debug 262 263.. _96Boards website: 264 https://www.96boards.org/product/avenger96/ 265 266.. _STM32MP157A on www.st.com: 267 https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-arm-cortex-mpus/stm32mp1-series/stm32mp157/stm32mp157a.html 268 269.. _STM32MP157A reference manual: 270 https://www.st.com/resource/en/reference_manual/DM00327659.pdf 271 272.. _Avenger96 board schematics: 273 https://www.96boards.org/documentation/consumer/avenger96/hardware-docs/files/avenger96-schematics.pdf 274 275.. _stm32mp1 developer package: 276 https://wiki.st.com/stm32mpu/index.php/STM32MP1_Developer_Package#Installing_the_SDK 277 278.. _stm32mp157 boot Cortex-M4 firmware: 279 https://wiki.st.com/stm32mpu/index.php/Linux_remoteproc_framework_overview#How_to_use_the_framework 280
