1# SPDX-License-Identifier: Apache-2.0
2
3zephyr_cc_option(-mlongcalls)
4
5zephyr_library()
6
7zephyr_library_sources(
8  cpu_idle.c
9  fatal.c
10  window_vectors.S
11  xtensa_asm2_util.S
12  irq_manage.c
13  thread.c
14  vector_handlers.c
15  )
16
17zephyr_library_sources_ifdef(CONFIG_XTENSA_USE_CORE_CRT1 crt1.S)
18zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
19zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
20zephyr_library_sources_ifdef(CONFIG_XTENSA_ENABLE_BACKTRACE xtensa_backtrace.c)
21zephyr_library_sources_ifdef(CONFIG_XTENSA_ENABLE_BACKTRACE debug_helpers_asm.S)
22zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c)
23zephyr_library_sources_ifdef(CONFIG_TIMING_FUNCTIONS timing.c)
24zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub.c)
25zephyr_library_sources_ifdef(CONFIG_XTENSA_MMU ptables.c mmu.c)
26zephyr_library_sources_ifdef(CONFIG_XTENSA_MPU mpu.c)
27zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S syscall_helper.c)
28zephyr_library_sources_ifdef(CONFIG_LLEXT elf.c)
29zephyr_library_sources_ifdef(CONFIG_SMP smp.c)
30zephyr_library_sources_ifdef(CONFIG_XTENSA_HIFI_SHARING xtensa_hifi.S)
31
32zephyr_library_sources_ifdef(
33  CONFIG_KERNEL_VM_USE_CUSTOM_MEM_RANGE_CHECK
34  mem_manage.c
35)
36
37if("${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "xcc")
38  zephyr_library_sources(xcc_stubs.c)
39endif()
40
41add_subdirectory(startup)
42
43# This produces a preprocessed and regenerated (in the sense of gcc
44# -dM, supported by all Xtensa toolchains) core-isa.h file available
45# as "core-isa-dM.h".  This can be easily parsed by non-C tooling.
46#
47# Note that this adds the SOC/HAL include directory explicitly, they
48# are the official places where we find core-isa.h. (Also that we
49# undefine __XCC_ because that compiler actually trips an error trying
50# to build this file to protect against mismatched versions.)
51set(CORE_ISA_DM ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/core-isa-dM.h)
52set(CORE_ISA_IN ${CMAKE_BINARY_DIR}/zephyr/include/generated/core-isa-dM.c)
53file(WRITE ${CORE_ISA_IN} "#include <xtensa/config/core-isa.h>\n")
54add_custom_command(OUTPUT ${CORE_ISA_DM}
55  COMMAND ${CMAKE_C_COMPILER} -E -dM -U__XCC__
56          -I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC}
57          -I${SOC_FULL_DIR}
58          ${CORE_ISA_IN} -o ${CORE_ISA_DM})
59
60if(CONFIG_USERSPACE AND NOT CONFIG_THREAD_LOCAL_STORAGE)
61  # It is possible that the SoC does not have THREADPTR.
62  # This means that we cannot use THREADPTR as a shortcut to
63  # in arch_is_user_context(). However, whether a SoC has
64  # THREADPTR is in core-isa.h which can be parsed in gen_zsr.py.
65  # There, if there is no THREADPTR, we need a scratch register
66  # so we can do arch_is_user_context() via syscall.
67  set(MAY_NEED_SYSCALL_SCRATCH_REG true)
68else()
69  # With thread local storage, the variable is_user_mode is
70  # stored in the thread's TLS area. There is no need for
71  # scratch register.
72  set(MAY_NEED_SYSCALL_SCRATCH_REG false)
73endif()
74
75# Generates a list of device-specific scratch register choices
76set(ZSR_H ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/zsr.h)
77add_custom_command(OUTPUT ${ZSR_H} DEPENDS ${CORE_ISA_DM}
78  COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gen_zsr.py
79                               $<$<BOOL:${CONFIG_XTENSA_MMU}>:--mmu>
80                               $<$<BOOL:${MAY_NEED_SYSCALL_SCRATCH_REG}>:--syscall-scratch>
81                               $<$<BOOL:${CONFIG_KERNEL_COHERENCE}>:--coherence>
82                               ${CORE_ISA_DM} ${ZSR_H})
83add_custom_target(zsr_h DEPENDS ${ZSR_H})
84add_dependencies(zephyr_interface zsr_h)
85
86unset(MAY_NEED_SYSCALL_SCRATCH_REG)
87
88# Similar: auto-generate interrupt handlers
89set(HANDLERS ${CMAKE_BINARY_DIR}/zephyr/include/generated/xtensa_handlers)
90
91add_custom_command(
92  OUTPUT ${HANDLERS}_tmp.c
93  COMMAND ${CMAKE_C_COMPILER} -E -U__XCC__
94	  -I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC}
95	  -o ${HANDLERS}_tmp.c
96	  - < ${CMAKE_CURRENT_SOURCE_DIR}/xtensa_intgen.tmpl)
97
98add_custom_command(
99  OUTPUT ${HANDLERS}.h
100  DEPENDS ${HANDLERS}_tmp.c
101  COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/xtensa_intgen.py
102          ${HANDLERS}_tmp.c > ${HANDLERS}.h)
103
104add_custom_target(xtensa_handlers_h DEPENDS ${HANDLERS}.h)
105add_dependencies(zephyr_interface xtensa_handlers_h)
106
107# Auto-generate interrupt vector entry
108set(VECS_LD ${CMAKE_BINARY_DIR}/zephyr/include/generated/xtensa_vectors.ld)
109add_custom_command(OUTPUT ${VECS_LD} DEPENDS ${CORE_ISA_DM}
110  COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gen_vectors.py
111          ${CORE_ISA_DM} > ${VECS_LD})
112add_custom_target(xtensa_vectors_ld DEPENDS ${VECS_LD})
113add_dependencies(zephyr_interface xtensa_vectors_ld)
114