1# Common architecture configuration options
2
3# Copyright (c) 2022, CSIRO.
4# SPDX-License-Identifier: Apache-2.0
5
6config SEMIHOST
7	bool "Semihosting support for ARM and RISC-V targets"
8	depends on ARM || ARM64 || RISCV
9	help
10	  Semihosting is a mechanism that enables code running on an ARM or
11	  RISC-V target to communicate and use the Input/Output facilities on
12	  a host computer that is running a debugger.
13	  Additional information can be found in:
14	  https://developer.arm.com/documentation/dui0471/m/what-is-semihosting-
15	  https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
16	  This option is compatible with hardware and with QEMU, through the
17	  (automatic) use of the -semihosting-config switch when invoking it.
18
19config LEGACY_MULTI_LEVEL_TABLE_GENERATION
20	bool "Auto generates the multi-level interrupt LUT (deprecated)"
21	default y
22	select DEPRECATED
23	depends on MULTI_LEVEL_INTERRUPTS
24	depends on !PLIC
25	depends on !NXP_IRQSTEER
26	depends on !RV32M1_INTMUX
27	depends on !CAVS_ICTL
28	depends on !DW_ICTL_ACE
29	depends on !DW_ICTL
30	help
31	  A make-shift Kconfig to continue generating the multi-level interrupt LUT
32	  with the legacy way using DT macros.
33