1 /*
2 * Copyright (c) 2020 Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/ztest.h>
8 #include <zephyr/drivers/spi.h>
9
10 #define TEST_FREQ_HZ 24000000U
11 #define W25Q128_JEDEC_ID 0x001840efU
12
13 #define TEST_BUF_SIZE 4096U
14 #define MAX_TX_BUF 2
15
16 #define SPI_STATUS2_QE 0x02U
17 #define SPI_READ_JEDEC_ID 0x9FU
18 #define SPI_READ_STATUS1 0x05U
19 #define SPI_READ_STATUS2 0x35U
20 #define SPI_WRITE_STATUS2 0x31U
21 #define SPI_WRITE_ENABLE_VS 0x50U
22 #define SPI_WRITE_ENABLE 0x06U
23 #define SPI_SECTOR_ERASE 0x20U
24 #define SPI_SINGLE_WRITE_DATA 0x02U
25 #define SPI_QUAD_WRITE_DATA 0x32U
26
27 /* bits[7:0] = spi opcode,
28 * bits[15:8] = bytes number of dummy clocks */
29 #define SPI_FAST_READ_DATA 0x080BU
30 #define SPI_DUAL_FAST_READ_DATA 0x083BU
31 #define SPI_QUAD_FAST_READ_DATA 0x086BU
32 #define SPI_OCTAL_QUAD_READ_DATA 0xE3U
33
34 #define BUF_SIZE 11
35 uint8_t buffer_tx[] = "0123456789\0";
36 #define BUF_SIZE_2 7
37 uint8_t buffer_tx_2[] = "abcdef\0";
38
39 #define SPI_TEST_ADDRESS 0x000010U
40 #define SPI_TEST_ADDRESS_2 0x000020U
41
42 static uint8_t safbuf[TEST_BUF_SIZE] __aligned(4);
43 static uint8_t safbuf2[TEST_BUF_SIZE] __aligned(4);
44 static const struct device *const spi_dev = DEVICE_DT_GET(DT_NODELABEL(spi0));
45 static struct spi_buf_set tx_bufs, rx_bufs;
46 static struct spi_buf txb[MAX_TX_BUF], rxb;
47 static struct spi_config spi_cfg_single, spi_cfg_dual, spi_cfg_quad;
48
49
spi_single_init(void)50 static void spi_single_init(void)
51 {
52 /* configure spi as single mode */
53 spi_cfg_single.frequency = TEST_FREQ_HZ;
54 spi_cfg_single.operation = SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB
55 | SPI_WORD_SET(8) | SPI_LINES_SINGLE;
56
57 zassert_true(device_is_ready(spi_dev), "SPI controller device is not ready");
58 }
59
60 /**
61 * @brief Test spi device
62 * @details
63 * - Find spi device
64 * - Read flash jedec id
65 */
ZTEST_USER(spi,test_spi_device)66 ZTEST_USER(spi, test_spi_device)
67 {
68 uint32_t jedec_id;
69 int ret;
70
71 /* read jedec id */
72 memset(safbuf, 0, TEST_BUF_SIZE);
73 safbuf[0] = SPI_READ_JEDEC_ID;
74 txb[0].buf = &safbuf;
75 txb[0].len = 1U;
76
77 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
78 tx_bufs.count = 1U;
79
80 jedec_id = 0U;
81 rxb.buf = &jedec_id;
82 rxb.len = 3U;
83
84 rx_bufs.buffers = (const struct spi_buf *)&rxb;
85 rx_bufs.count = 1U;
86
87 ret = spi_transceive(spi_dev,
88 (const struct spi_config *)&spi_cfg_single,
89 (const struct spi_buf_set *)&tx_bufs,
90 (const struct spi_buf_set *)&rx_bufs);
91 zassert_true(ret == 0, "Read JEDEC ID spi_transceive failure: "
92 "error %d", ret);
93 zassert_true(jedec_id == W25Q128_JEDEC_ID, "JEDEC ID doesn't match");
94 }
95
96 /**
97 * @brief Test spi sector erase
98 * @details
99 * - write enable
100 * - erase data in flash device
101 * - read register1 and wait for erase operation completed
102 */
ZTEST_USER(spi_sector_erase,test_spi_sector_erase)103 ZTEST_USER(spi_sector_erase, test_spi_sector_erase)
104 {
105 int ret;
106
107 /* write enable */
108 memset(safbuf, 0, TEST_BUF_SIZE);
109 safbuf[0] = SPI_WRITE_ENABLE;
110 txb[0].buf = &safbuf;
111 txb[0].len = 1U;
112
113 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
114 tx_bufs.count = 1U;
115
116 rx_bufs.buffers = NULL;
117 rx_bufs.count = 0U;
118
119 ret = spi_transceive(spi_dev,
120 (const struct spi_config *)&spi_cfg_single,
121 (const struct spi_buf_set *)&tx_bufs,
122 (const struct spi_buf_set *)&rx_bufs);
123 zassert_true(ret == 0, "Send write enable spi_transceive failure: "
124 "error %d", ret);
125
126 /* erase data start from address 0x000010 */
127 safbuf[0] = SPI_SECTOR_ERASE;
128 safbuf[1] = SPI_TEST_ADDRESS & 0xFFFFFFU;
129
130 txb[0].buf = &safbuf;
131 txb[0].len = 4;
132
133 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
134 tx_bufs.count = 1U;
135
136 rx_bufs.buffers = NULL;
137 rx_bufs.count = 0U;
138
139 ret = spi_transceive(spi_dev,
140 (const struct spi_config *)&spi_cfg_single,
141 (const struct spi_buf_set *)&tx_bufs,
142 (const struct spi_buf_set *)&rx_bufs);
143 zassert_true(ret == 0, "Send sector erase data spi_transceive failure: "
144 "error %d", ret);
145
146 /* read register1 to check whether erase operation completed */
147 safbuf[0] = SPI_READ_STATUS1;
148
149 txb[0].buf = &safbuf;
150 txb[0].len = 1;
151
152 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
153 tx_bufs.count = 1U;
154
155 memset(safbuf2, 1U, 1U);
156 rxb.buf = &safbuf2;
157 rxb.len = 1U;
158
159 rx_bufs.buffers = (const struct spi_buf *)&rxb;
160 rx_bufs.count = 1U;
161
162 /* waiting for erase operation completed */
163 while (safbuf2[0]) {
164 ret = spi_transceive(spi_dev,
165 (const struct spi_config *)&spi_cfg_single,
166 (const struct spi_buf_set *)&tx_bufs,
167 (const struct spi_buf_set *)&rx_bufs);
168 zassert_true(ret == 0, "Send read register1 spi_transceive "
169 "failure: error %d", ret);
170 }
171 }
172
173 /**
174 * @brief Write data into flash using spi api
175 * @details
176 * - flash write enable
177 * - write data into flash using spi api
178 */
test_spi_single_write(void)179 static void test_spi_single_write(void)
180 {
181 int ret;
182
183 /* write enable */
184 memset(safbuf, 0, TEST_BUF_SIZE);
185 safbuf[0] = SPI_WRITE_ENABLE;
186 txb[0].buf = &safbuf;
187 txb[0].len = 1U;
188
189 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
190 tx_bufs.count = 1U;
191
192 rx_bufs.buffers = NULL;
193 rx_bufs.count = 0U;
194
195 ret = spi_transceive(spi_dev,
196 (const struct spi_config *)&spi_cfg_single,
197 (const struct spi_buf_set *)&tx_bufs,
198 (const struct spi_buf_set *)&rx_bufs);
199 zassert_true(ret == 0, "Send write enable spi_transceive failure: "
200 "error %d", ret);
201
202 /* write data start from address 0x000010 */
203 safbuf[0] = SPI_SINGLE_WRITE_DATA;
204 safbuf[1] = SPI_TEST_ADDRESS & 0xFFFFFFU;
205 memcpy(&safbuf[4], buffer_tx, BUF_SIZE);
206
207 txb[0].buf = &safbuf;
208 txb[0].len = 4 + BUF_SIZE;
209
210 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
211 tx_bufs.count = 1U;
212
213 rx_bufs.buffers = NULL;
214 rx_bufs.count = 0U;
215
216 ret = spi_transceive(spi_dev,
217 (const struct spi_config *)&spi_cfg_single,
218 (const struct spi_buf_set *)&tx_bufs,
219 (const struct spi_buf_set *)&rx_bufs);
220 zassert_true(ret == 0, "Send write data spi_transceive failure: "
221 "error %d", ret);
222 }
223
224 /**
225 * @brief Read data from flash using spi single mode
226 * @details
227 * - read data using spi single mode
228 * - check read buffer data whether correct
229 */
ZTEST_USER(spi,test_spi_single_read)230 ZTEST_USER(spi, test_spi_single_read)
231 {
232 int ret;
233 uint8_t cnt = 0;
234 uint16_t spi_opcode;
235
236 spi_opcode = SPI_FAST_READ_DATA;
237
238 /* read data using spi single mode */
239 /* set the spi operation code and address */
240 memset(safbuf, 0, TEST_BUF_SIZE);
241 safbuf[0] = spi_opcode & 0xFFU;
242 safbuf[1] = SPI_TEST_ADDRESS & 0xFFFFFFU;
243
244 txb[cnt].buf = &safbuf;
245 txb[cnt].len = 4U;
246
247 /* set the dummy clocks */
248 if (spi_opcode & 0xFF00U) {
249 cnt++;
250 txb[cnt].buf = NULL;
251 txb[cnt].len = (spi_opcode >> 8) & 0xFFU;
252 }
253
254 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
255 tx_bufs.count = cnt + 1;
256
257 memset(safbuf2, 0, BUF_SIZE);
258 rxb.buf = &safbuf2;
259 rxb.len = BUF_SIZE;
260
261 rx_bufs.buffers = (const struct spi_buf *)&rxb;
262 rx_bufs.count = 1U;
263
264 ret = spi_transceive(spi_dev,
265 (const struct spi_config *)&spi_cfg_single,
266 (const struct spi_buf_set *)&tx_bufs,
267 (const struct spi_buf_set *)&rx_bufs);
268 zassert_true(ret == 0, "Send fast read data spi_transceive failure: "
269 "error %d", ret);
270
271 /* check read buffer data whether correct */
272 zassert_true(memcmp(buffer_tx, safbuf2, BUF_SIZE) == 0,
273 "Buffer read data is different to write data");
274 }
275
spi_dual_init(void)276 static void spi_dual_init(void)
277 {
278 /* configure spi dual mode */
279 spi_cfg_dual.frequency = TEST_FREQ_HZ;
280 spi_cfg_dual.operation = SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB
281 | SPI_WORD_SET(8) | SPI_LINES_DUAL;
282
283 zassert_true(device_is_ready(spi_dev), "SPI controller device is not ready");
284 }
285
286 /**
287 * @brief Read data from flash using spi dual mode
288 * @details
289 * - read data using spi dual mode
290 * - check read buffer data whether correct
291 */
ZTEST_USER(spi,test_spi_dual_read)292 ZTEST_USER(spi, test_spi_dual_read)
293 {
294 int ret;
295 uint8_t cnt = 0;
296 uint16_t spi_opcode;
297
298 spi_dual_init();
299
300 spi_opcode = SPI_DUAL_FAST_READ_DATA;
301
302 /* read data using spi dual mode */
303 /* set the spi operation code and address */
304 memset(safbuf, 0, TEST_BUF_SIZE);
305 safbuf[0] = spi_opcode & 0xFFU;
306 safbuf[1] = SPI_TEST_ADDRESS & 0xFFFFFFU;
307
308 txb[cnt].buf = &safbuf;
309 txb[cnt].len = 4U;
310
311 /* set the dummy clocks */
312 if (spi_opcode & 0xFF00U) {
313 cnt++;
314 txb[cnt].buf = NULL;
315 txb[cnt].len = (spi_opcode >> 8) & 0xFFU;
316 }
317
318 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
319 tx_bufs.count = cnt + 1;
320
321 /* send opcode and address using single mode */
322 spi_cfg_single.operation |= SPI_HOLD_ON_CS;
323 ret = spi_transceive(spi_dev,
324 (const struct spi_config *)&spi_cfg_single,
325 (const struct spi_buf_set *)&tx_bufs, NULL);
326 zassert_true(ret == 0, "Send fast read data spi_transceive failure: "
327 "error %d", ret);
328
329 memset(safbuf2, 0, BUF_SIZE);
330 rxb.buf = &safbuf2;
331 rxb.len = BUF_SIZE;
332
333 rx_bufs.buffers = (const struct spi_buf *)&rxb;
334 rx_bufs.count = 1U;
335
336 /* get read data using dual mode */
337 ret = spi_transceive(spi_dev,
338 (const struct spi_config *)&spi_cfg_dual,
339 NULL, (const struct spi_buf_set *)&rx_bufs);
340 zassert_true(ret == 0, "Receive fast read data spi_transceive failure: "
341 "error %d", ret);
342
343 /* check read buffer data whether correct */
344 zassert_true(memcmp(buffer_tx, safbuf2, BUF_SIZE) == 0,
345 "Buffer read data is different to write data");
346
347 /* release spi device */
348 spi_cfg_single.operation = SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB
349 | SPI_WORD_SET(8) | SPI_LINES_SINGLE;
350 ret = spi_release(spi_dev, (const struct spi_config *)&spi_cfg_single);
351 zassert_true(ret == 0, "Spi release failure: error %d", ret);
352 }
353
354 /**
355 * @brief Write data into flash using spi quad mode
356 * @details
357 * - check and make sure spi quad mode is enabled
358 * - write data using spi quad mode
359 */
test_spi_quad_write(void)360 static void test_spi_quad_write(void)
361 {
362 int ret;
363 uint8_t spi_status2;
364
365 /* read register2 to judge whether quad mode is enabled */
366 safbuf[0] = SPI_READ_STATUS2;
367 txb[0].buf = &safbuf;
368 txb[0].len = 1U;
369
370 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
371 tx_bufs.count = 1U;
372
373 memset(safbuf2, 0, 1U);
374 rxb.buf = &safbuf2;
375 rxb.len = 1U;
376
377 rx_bufs.buffers = (const struct spi_buf *)&rxb;
378 rx_bufs.count = 1U;
379
380 ret = spi_transceive(spi_dev,
381 (const struct spi_config *)&spi_cfg_single,
382 (const struct spi_buf_set *)&tx_bufs,
383 (const struct spi_buf_set *)&rx_bufs);
384 zassert_true(ret == 0, "Read register2 status spi_transceive failure: "
385 "error %d", ret);
386
387 spi_status2 = safbuf2[0];
388 /* set register2 QE=1 to enable quad mode */
389 if ((spi_status2 & SPI_STATUS2_QE) == 0U) {
390 safbuf[0] = SPI_WRITE_ENABLE_VS;
391
392 txb[0].buf = &safbuf;
393 txb[0].len = 1U;
394
395 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
396 tx_bufs.count = 1U;
397
398 rx_bufs.buffers = NULL;
399 rx_bufs.count = 0U;
400
401 ret = spi_transceive(spi_dev,
402 (const struct spi_config *)&spi_cfg_single,
403 (const struct spi_buf_set *)&tx_bufs,
404 (const struct spi_buf_set *)&rx_bufs);
405 zassert_true(ret == 0,
406 "Send write enable volatile spi_transceive failure: "
407 "error %d", ret);
408
409 safbuf[0] = SPI_WRITE_STATUS2;
410 safbuf[1] = spi_status2 | SPI_STATUS2_QE;
411
412 txb[0].buf = &safbuf;
413 txb[0].len = 2U;
414
415 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
416 tx_bufs.count = 1U;
417
418 rx_bufs.buffers = NULL;
419 rx_bufs.count = 0U;
420
421 ret = spi_transceive(spi_dev,
422 (const struct spi_config *)&spi_cfg_single,
423 (const struct spi_buf_set *)&tx_bufs,
424 (const struct spi_buf_set *)&rx_bufs);
425 zassert_true(ret == 0,
426 "Write spi status2 QE=1 spi_transceive failure: "
427 "error %d", ret);
428
429 /* read register2 to confirm quad mode is enabled */
430 safbuf[0] = SPI_READ_STATUS2;
431 txb[0].buf = &safbuf;
432 txb[0].len = 1U;
433
434 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
435 tx_bufs.count = 1U;
436
437 memset(safbuf2, 0, 1U);
438 rxb.buf = &safbuf2;
439 rxb.len = 1U;
440
441 rx_bufs.buffers = (const struct spi_buf *)&rxb;
442 rx_bufs.count = 1U;
443
444 ret = spi_transceive(spi_dev,
445 (const struct spi_config *)&spi_cfg_single,
446 (const struct spi_buf_set *)&tx_bufs,
447 (const struct spi_buf_set *)&rx_bufs);
448 zassert_true(ret == 0, "Read register2 status spi_transceive failure: "
449 "error %d", ret);
450
451 spi_status2 = safbuf2[0];
452 zassert_true((spi_status2 & SPI_STATUS2_QE) == SPI_STATUS2_QE,
453 "Enable QSPI mode failure");
454 }
455
456 /* write enable */
457 safbuf[0] = SPI_WRITE_ENABLE;
458 txb[0].buf = &safbuf;
459 txb[0].len = 1U;
460
461 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
462 tx_bufs.count = 1U;
463
464 rx_bufs.buffers = NULL;
465 rx_bufs.count = 0U;
466
467 ret = spi_transceive(spi_dev,
468 (const struct spi_config *)&spi_cfg_single,
469 (const struct spi_buf_set *)&tx_bufs,
470 (const struct spi_buf_set *)&rx_bufs);
471 zassert_true(ret == 0, "Send write enable spi_transceive failure: "
472 "error %d", ret);
473
474 /* configure spi quad mode */
475 spi_cfg_quad.frequency = TEST_FREQ_HZ;
476 spi_cfg_quad.operation = SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB
477 | SPI_WORD_SET(8) | SPI_LINES_QUAD;
478
479 /* write data using spi quad mode */
480 /* send quad write opcode and address using single mode */
481 memset(safbuf, 0, TEST_BUF_SIZE);
482 safbuf[0] = SPI_QUAD_WRITE_DATA;
483 safbuf[1] = SPI_TEST_ADDRESS_2 & 0xFFFFFFU;
484
485 txb[0].buf = &safbuf;
486 txb[0].len = 4;
487
488 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
489 tx_bufs.count = 1U;
490
491 rx_bufs.buffers = NULL;
492 rx_bufs.count = 0U;
493
494 spi_cfg_single.operation |= SPI_HOLD_ON_CS;
495 ret = spi_transceive(spi_dev,
496 (const struct spi_config *)&spi_cfg_single,
497 (const struct spi_buf_set *)&tx_bufs,
498 (const struct spi_buf_set *)&rx_bufs);
499 zassert_true(ret == 0, "Send quad write data spi_transceive failure: "
500 "error %d", ret);
501
502 /* send data using quad mode */
503 memset(safbuf, 0, TEST_BUF_SIZE);
504 memcpy(&safbuf[0], buffer_tx_2, BUF_SIZE_2);
505
506 txb[0].buf = &safbuf;
507 txb[0].len = BUF_SIZE_2;
508
509 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
510 tx_bufs.count = 1U;
511
512 rx_bufs.buffers = NULL;
513 rx_bufs.count = 0U;
514
515 ret = spi_transceive(spi_dev,
516 (const struct spi_config *)&spi_cfg_quad,
517 (const struct spi_buf_set *)&tx_bufs,
518 (const struct spi_buf_set *)&rx_bufs);
519 zassert_true(ret == 0, "Send quad write data spi_transceive failure: "
520 "error %d", ret);
521
522 spi_cfg_single.operation = SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB
523 | SPI_WORD_SET(8) | SPI_LINES_SINGLE;
524 ret = spi_release(spi_dev, (const struct spi_config *)&spi_cfg_single);
525 zassert_true(ret == 0, "Spi release failure: error %d", ret);
526 }
527
528 /**
529 * @brief Read data from flash using spi quad mode
530 * @details
531 * - read data using spi quad mode
532 * - check read buffer data whether correct
533 */
ZTEST_USER(spi_quad,test_spi_quad_read)534 ZTEST_USER(spi_quad, test_spi_quad_read)
535 {
536 int ret;
537 uint8_t cnt = 0;
538 uint16_t spi_opcode;
539
540 spi_opcode = SPI_QUAD_FAST_READ_DATA;
541
542 /* read data using spi quad mode */
543 /* set the spi operation code and address */
544 memset(safbuf, 0, TEST_BUF_SIZE);
545 safbuf[0] = spi_opcode & 0xFFU;
546 safbuf[1] = SPI_TEST_ADDRESS_2 & 0xFFFFFFU;
547
548 txb[cnt].buf = &safbuf;
549 txb[cnt].len = 4U;
550
551 /* set the dummy clocks */
552 if (spi_opcode & 0xFF00U) {
553 cnt++;
554 txb[cnt].buf = NULL;
555 txb[cnt].len = (spi_opcode >> 8) & 0xFFU;
556 }
557
558 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
559 tx_bufs.count = cnt + 1;
560
561 /* send opcode and address using single mode */
562 spi_cfg_single.operation |= SPI_HOLD_ON_CS;
563 ret = spi_transceive(spi_dev,
564 (const struct spi_config *)&spi_cfg_single,
565 (const struct spi_buf_set *)&tx_bufs, NULL);
566 zassert_true(ret == 0, "Send fast read data spi_transceive failure: "
567 "error %d", ret);
568
569 memset(safbuf2, 0, TEST_BUF_SIZE);
570 rxb.buf = &safbuf2;
571 rxb.len = BUF_SIZE_2;
572
573 rx_bufs.buffers = (const struct spi_buf *)&rxb;
574 rx_bufs.count = 1U;
575
576 /* get read data using quad mode */
577 ret = spi_transceive(spi_dev,
578 (const struct spi_config *)&spi_cfg_quad,
579 NULL, (const struct spi_buf_set *)&rx_bufs);
580 zassert_true(ret == 0, "Receive fast read data spi_transceive failure: "
581 "error %d", ret);
582
583 /* check read buffer data whether correct */
584 zassert_true(memcmp(buffer_tx_2, safbuf2, BUF_SIZE_2) == 0,
585 "Buffer read data is different to write data");
586
587 /* release spi device */
588 spi_cfg_single.operation = SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB
589 | SPI_WORD_SET(8) | SPI_LINES_SINGLE;
590 ret = spi_release(spi_dev, (const struct spi_config *)&spi_cfg_single);
591 zassert_true(ret == 0, "Spi release failure: error %d", ret);
592 }
593
594 /**
595 * @brief Read data from flash using spi octal quad mode
596 * @details
597 * - read data using spi octal quad mode
598 * - check read buffer data whether correct
599 */
ZTEST_USER(spi_quad,test_spi_octal_read)600 ZTEST_USER(spi_quad, test_spi_octal_read)
601 {
602 int ret;
603
604 /* read data using spi octal quad mode */
605 /* send octal read opcode using single mode */
606 memset(safbuf, 0, TEST_BUF_SIZE);
607 safbuf[0] = SPI_OCTAL_QUAD_READ_DATA;
608
609 txb[0].buf = &safbuf;
610 txb[0].len = 1;
611
612 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
613 tx_bufs.count = 1U;
614
615 rx_bufs.buffers = NULL;
616 rx_bufs.count = 0U;
617
618 spi_cfg_single.operation |= SPI_HOLD_ON_CS;
619 ret = spi_transceive(spi_dev,
620 (const struct spi_config *)&spi_cfg_single,
621 (const struct spi_buf_set *)&tx_bufs,
622 (const struct spi_buf_set *)&rx_bufs);
623 zassert_true(ret == 0, "Send octal quad read opcode "
624 "spi_transceive failure: error %d", ret);
625
626 /* send address using quad mode */
627 safbuf[0] = SPI_TEST_ADDRESS & 0xFFFFF0U;
628 safbuf[3] = 0xFFU;
629 txb[0].buf = &safbuf;
630 txb[0].len = 4;
631
632 tx_bufs.buffers = (const struct spi_buf *)&txb[0];
633 tx_bufs.count = 1U;
634
635 memset(safbuf2, 0, TEST_BUF_SIZE);
636 rxb.buf = &safbuf2;
637 rxb.len = BUF_SIZE;
638
639 rx_bufs.buffers = (const struct spi_buf *)&rxb;
640 rx_bufs.count = 1U;
641
642 ret = spi_transceive(spi_dev,
643 (const struct spi_config *)&spi_cfg_quad,
644 (const struct spi_buf_set *)&tx_bufs,
645 (const struct spi_buf_set *)&rx_bufs);
646 zassert_true(ret == 0, "Send quad read address spi_transceive "
647 "failure: error %d", ret);
648
649 /* check read buffer data whether correct */
650 zassert_true(memcmp(buffer_tx, safbuf2, BUF_SIZE) == 0,
651 "Buffer read data is different to write data");
652
653 /* release spi device */
654 spi_cfg_single.operation = SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB
655 | SPI_WORD_SET(8) | SPI_LINES_SINGLE;
656 ret = spi_release(spi_dev, (const struct spi_config *)&spi_cfg_single);
657 zassert_true(ret == 0, "Spi release failure: error %d", ret);
658 }
659
660
spi_setup(void)661 void *spi_setup(void)
662 {
663 spi_single_init();
664
665 return NULL;
666 }
667
spi_single_setup(void)668 void *spi_single_setup(void)
669 {
670 spi_single_init();
671
672 /* The writing test goes
673 * first berfore testing
674 * the reading.
675 */
676 test_spi_single_write();
677
678 return NULL;
679 }
680
spi_quad_setup(void)681 void *spi_quad_setup(void)
682 {
683 spi_dual_init();
684
685 /* The writing test goes
686 * first berfore testing
687 * the reading.
688 */
689 test_spi_quad_write();
690
691 return NULL;
692 }
693
694 ZTEST_SUITE(spi, NULL, spi_single_setup, NULL, NULL, NULL);
695 ZTEST_SUITE(spi_quad, NULL, spi_quad_setup, NULL, NULL, NULL);
696 ZTEST_SUITE(spi_sector_erase, NULL, spi_setup, NULL, NULL, NULL);
697
