1 /*
2  * Copyright 2021, 2023 NXP
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_SOC_NXP_ADSP_MEMORY_H_
8 #define ZEPHYR_SOC_NXP_ADSP_MEMORY_H_
9 
10 #define PLATFORM_CORE_COUNT 1
11 
12 /** Id of master DSP core */
13 #define PLATFORM_PRIMARY_CORE_ID	0
14 
15 #define IRAM_RESERVE_HEADER_SPACE	0x400
16 
17 #define IRAM_BASE	0x3B6F8000
18 #define IRAM_SIZE	0x800
19 
20 #define SDRAM0_BASE	0x92400000
21 #define SDRAM0_SIZE	0x800000
22 
23 #define SDRAM1_BASE	0x92C00000
24 #define SDRAM1_SIZE	0x800000
25 
26 /* The reset vector address in SRAM and its size */
27 #define MEM_RESET_TEXT_SIZE			0x2E0
28 #define MEM_RESET_LIT_SIZE			0x120
29 
30 /* This is the base address of all the vectors defined in IRAM */
31 #define XCHAL_VECBASE_RESET_PADDR_IRAM \
32 		(IRAM_BASE + IRAM_RESERVE_HEADER_SPACE)
33 
34 #define MEM_VECBASE_LIT_SIZE			0x178
35 
36 /*
37  * EXCEPTIONS and VECTORS
38  */
39 #define XCHAL_RESET_VECTOR0_PADDR_IRAM	0x3B6F8000
40 
41 /* Vector and literal sizes */
42 #define MEM_VECT_LIT_SIZE			0x4
43 #define MEM_VECT_TEXT_SIZE			0x1C
44 #define MEM_VECT_SIZE				(MEM_VECT_TEXT_SIZE +\
45 									 MEM_VECT_LIT_SIZE)
46 
47 /* The addresses of the vectors.
48  * Only the mem_error vector continues to point to its ROM address.
49  */
50 #define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM \
51 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x17C)
52 
53 #define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM \
54 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x19C)
55 
56 #define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM \
57 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1BC)
58 
59 #define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM \
60 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1DC)
61 
62 #define XCHAL_KERNEL_VECTOR_PADDR_IRAM \
63 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1FC)
64 
65 #define XCHAL_USER_VECTOR_PADDR_IRAM \
66 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x21C)
67 
68 #define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM \
69 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x23C)
70 
71 /* Location for the intList section which is later used to construct the
72  * Interrupt Descriptor Table (IDT). This is a bogus address as this
73  * section will be stripped off in the final image.
74  */
75 #define IDT_BASE	(IRAM_BASE + IRAM_SIZE)
76 
77 /* size of the Interrupt Descriptor Table (IDT) */
78 #define IDT_SIZE	0x2000
79 
80 /* physical DSP addresses */
81 #define IRAM_BASE	0x3B6F8000
82 #define IRAM_SIZE	0x800
83 
84 #define DRAM0_BASE	0x3B6E8000
85 #define DRAM0_SIZE	0x8000
86 
87 #define DRAM1_BASE	0x3B6F0000
88 #define DRAM1_SIZE	0x8000
89 
90 #define SDRAM0_BASE	0x92400000
91 #define SDRAM0_SIZE	0x800000
92 
93 #define SDRAM1_BASE	0x92C00000
94 #define SDRAM1_SIZE	0x800000
95 
96 #define XSHAL_MU2_SIDEB_BYPASS_PADDR 0x30E70000
97 #define MU_BASE		XSHAL_MU2_SIDEB_BYPASS_PADDR
98 
99 #define SDMA2_BASE	0x30E10000
100 #define SDMA2_SIZE	0x10000
101 
102 #define SDMA3_BASE	0x30E00000
103 #define SDMA3_SIZE	0x10000
104 
105 #define SAI_1_BASE	0x30C10000
106 #define SAI_1_SIZE	0x00010000
107 
108 #define SAI_3_BASE	0x30C30000
109 #define SAI_3_SIZE	0x00010000
110 #define UUID_ENTRY_ELF_BASE	0x1FFFA000
111 #define UUID_ENTRY_ELF_SIZE	0x6000
112 
113 #define LOG_ENTRY_ELF_BASE	0x20000000
114 #define LOG_ENTRY_ELF_SIZE	0x2000000
115 
116 #define EXT_MANIFEST_ELF_BASE	(LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
117 #define EXT_MANIFEST_ELF_SIZE	0x2000000
118 
119 /*
120  * The Heap and Stack on i.MX8 are organized like this :-
121  *
122  * +--------------------------------------------------------------------------+
123  * | Offset              | Region         |  Size                             |
124  * +---------------------+----------------+-----------------------------------+
125  * | SDRAM_BASE          | RO Data        |  SOF_DATA_SIZE                    |
126  * |                     | Data           |                                   |
127  * |                     | BSS            |                                   |
128  * +---------------------+----------------+-----------------------------------+
129  * | HEAP_SYSTEM_BASE    | System Heap    |  HEAP_SYSTEM_SIZE                 |
130  * +---------------------+----------------+-----------------------------------+
131  * | HEAP_RUNTIME_BASE   | Runtime Heap   |  HEAP_RUNTIME_SIZE                |
132  * +---------------------+----------------+-----------------------------------+
133  * | HEAP_BUFFER_BASE    | Module Buffers |  HEAP_BUFFER_SIZE                 |
134  * +---------------------+----------------+-----------------------------------+
135  * | SOF_STACK_END       | Stack          |  SOF_STACK_SIZE                   |
136  * +---------------------+----------------+-----------------------------------+
137  * | SOF_STACK_BASE      |                |                                   |
138  * +---------------------+----------------+-----------------------------------+
139  */
140 
141 #define SRAM_OUTBOX_BASE	SDRAM1_BASE
142 #define SRAM_OUTBOX_SIZE	0x1000
143 #define SRAM_OUTBOX_OFFSET	0
144 
145 #define SRAM_INBOX_BASE		(SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE)
146 #define SRAM_INBOX_SIZE		0x1000
147 #define SRAM_INBOX_OFFSET	SRAM_OUTBOX_SIZE
148 
149 #define SRAM_DEBUG_BASE		(SRAM_INBOX_BASE + SRAM_INBOX_SIZE)
150 #define SRAM_DEBUG_SIZE		0x800
151 #define SRAM_DEBUG_OFFSET	(SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE)
152 
153 #define SRAM_EXCEPT_BASE	(SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE)
154 #define SRAM_EXCEPT_SIZE	0x800
155 #define SRAM_EXCEPT_OFFSET	(SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE)
156 
157 #define SRAM_STREAM_BASE	(SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE)
158 #define SRAM_STREAM_SIZE	0x1000
159 #define SRAM_STREAM_OFFSET	(SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE)
160 
161 #define SRAM_TRACE_BASE		(SRAM_STREAM_BASE + SRAM_STREAM_SIZE)
162 #define SRAM_TRACE_SIZE		0x1000
163 #define SRAM_TRACE_OFFSET	(SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE)
164 
165 #define SOF_MAILBOX_SIZE	(SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \
166 				 + SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \
167 				 + SRAM_STREAM_SIZE + SRAM_TRACE_SIZE)
168 
169 #endif /* ZEPHYR_SOC_NXP_ADSP_MEMORY_H_ */
170