1/*
2 * Copyright (c) 2021 Telink Semiconductor
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#define NDS_MCACHE_CTL               0x7CA
8#define NDS_MMISC_CTL                0x7D0
9
10#include <zephyr/toolchain.h>
11
12	.option push
13	.option norelax
14	.org 0x0
15
16/* exports */
17GTEXT(entry)
18
19SECTION_FUNC(init, init)
20entry:
21
22	j start
23
24	.org 0x20
25	.word ('T'<<24 | 'L'<<16 | 'N'<<8 | 'K')
26
27	.org 0x26
28	.short (0x173B)
29
30	.align 2
31
32start:
33
34	/* Enable I/D-Cache */
35	csrr   t0,  NDS_MCACHE_CTL
36	ori    t0,  t0,  1        #/I-Cache
37	ori    t0,  t0,  2        #/D-Cache
38	csrw   NDS_MCACHE_CTL,  t0
39	fence.i
40
41	/* Enable misaligned access and non-blocking load */
42	li t0, (1 << 8) | (1 << 6)
43	csrs NDS_MMISC_CTL, t0
44
45_ZERO_AES:
46	lui    t0, 0
47	la     t2, _AES_DATA_VMA_START
48	la     t3, _AES_DATA_VMA_END
49_ZERO_AES_BEGIN:
50	bleu   t3, t2, _RETENTION_DATA_INIT
51	sw     t0, 0(t2)
52	addi   t2, t2, 4
53	j      _ZERO_AES_BEGIN
54
55_RETENTION_DATA_INIT:
56	la     t1, _RETENTION_DATA_LMA_START
57	la     t2, _RETENTION_DATA_VMA_START
58	la     t3, _RETENTION_DATA_VMA_END
59_RETENTION_DATA_INIT_BEGIN:
60	bleu   t3, t2, _RAMCODE_INIT
61	lw     t0, 0(t1)
62	sw     t0, 0(t2)
63	addi   t1, t1, 4
64	addi   t2, t2, 4
65	j      _RETENTION_DATA_INIT_BEGIN
66
67_RAMCODE_INIT:
68	la     t1, _RAMCODE_LMA_START
69	la     t2, _RAMCODE_VMA_START
70	la     t3, _RAMCODE_VMA_END
71_RAMCODE_INIT_BEGIN:
72	bleu   t3, t2, _START
73	lw     t0, 0(t1)
74	sw     t0, 0(t2)
75	addi   t1, t1, 4
76	addi   t2, t2, 4
77	j      _RAMCODE_INIT_BEGIN
78
79_START:
80	j __start
81
82	.option pop
83