1# -------------------------------------------------------------------------- #
2#
3# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
4# Your use of Altera Corporation's design tools, logic functions
5# and other software and tools, and its AMPP partner logic
6# functions, and any output files from any of the foregoing
7# (including device programming or simulation files), and any
8# associated documentation or information are expressly subject
9# to the terms and conditions of the Altera Program License
10# Subscription Agreement, the Altera Quartus Prime License Agreement,
11# the Altera MegaCore Function License Agreement, or other
12# applicable license agreement, including, without limitation,
13# that your use is for the sole purpose of programming logic
14# devices manufactured by Altera and sold by Altera or its
15# authorized distributors.  Please refer to the applicable
16# agreement for further details.
17#
18# -------------------------------------------------------------------------- #
19#
20# Quartus Prime
21# Version 16.0.0 Build 208 04/06/2016 SJ Standard Edition
22# Date created = 16:01:48  April 27, 2016
23#
24# -------------------------------------------------------------------------- #
25#
26# Notes:
27#
28# 1) The default values for assignments are stored in the file:
29#		ghrd_10m50da_assignment_defaults.qdf
30#    If this file doesn't exist, see file:
31#		assignment_defaults.qdf
32#
33# 2) Altera recommends that you do not modify this file. This
34#    file is updated automatically by the Quartus Prime software
35#    and any changes you make may be lost or overwritten.
36#
37# -------------------------------------------------------------------------- #
38
39
40set_global_assignment -name FAMILY "MAX 10"
41set_global_assignment -name DEVICE 10M50DAF484C6GES
42set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
43set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:01:48  APRIL 27, 2016"
44set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Standard Edition"
45set_global_assignment -name TOP_LEVEL_ENTITY ghrd_10m50da_top
46set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
47set_global_assignment -name UNIPHY_SEQUENCER_DQS_CONFIG_ENABLE ON
48set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
49set_global_assignment -name UNIPHY_TEMP_VER_CODE 1590306432
50set_global_assignment -name ECO_REGENERATE_REPORT ON
51set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
52set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
53set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
54set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
55set_global_assignment -name ENABLE_SIGNALTAP ON
56set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
57set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
58set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
59set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
60set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
61set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
62set_global_assignment -name QII_AUTO_PACKED_REGISTERS NORMAL
63set_global_assignment -name MUX_RESTRUCTURE OFF
64set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
65set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
66set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
67set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
68set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
69set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE"
70set_global_assignment -name ENABLE_OCT_DONE OFF
71set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
72set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
73set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
74set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
75set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
76set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
77set_global_assignment -name SEED 16
78set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
79set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
80set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
81set_location_assignment PIN_N14 -to clk_ddr3_100_p
82set_location_assignment PIN_M8 -to clk_25_max10
83set_location_assignment PIN_N5 -to clk_10_adc
84set_location_assignment PIN_P11 -to clk_lvds_125_p
85set_location_assignment PIN_T20 -to user_led[0]
86set_location_assignment PIN_U22 -to user_led[1]
87set_location_assignment PIN_U21 -to user_led[2]
88set_location_assignment PIN_AA21 -to user_led[3]
89set_location_assignment PIN_AA22 -to user_led[4]
90set_location_assignment PIN_L22 -to user_pb[0]
91set_location_assignment PIN_M21 -to user_pb[1]
92set_location_assignment PIN_M22 -to user_pb[2]
93set_location_assignment PIN_N21 -to user_pb[3]
94set_location_assignment PIN_H21 -to user_dipsw[0]
95set_location_assignment PIN_H22 -to user_dipsw[1]
96set_location_assignment PIN_J21 -to user_dipsw[2]
97set_location_assignment PIN_J22 -to user_dipsw[3]
98set_location_assignment PIN_G19 -to user_dipsw[4]
99set_location_assignment PIN_Y19 -to uart_rx
100set_location_assignment PIN_W18 -to uart_tx
101set_location_assignment PIN_Y6 -to enet_mdc
102set_location_assignment PIN_Y5 -to enet_mdio
103set_location_assignment PIN_T5 -to enet_gtx_clk
104set_location_assignment PIN_V7 -to enet_intn
105set_location_assignment PIN_V8 -to enet_resetn
106set_location_assignment PIN_P3 -to enet_rx_clk
107set_location_assignment PIN_P1 -to enet_rx_col
108set_location_assignment PIN_N8 -to enet_rx_crs
109set_location_assignment PIN_N9 -to enet_rx_d[0]
110set_location_assignment PIN_T1 -to enet_rx_d[1]
111set_location_assignment PIN_N1 -to enet_rx_d[2]
112set_location_assignment PIN_T3 -to enet_rx_d[3]
113set_location_assignment PIN_T2 -to enet_rx_dv
114set_location_assignment PIN_U2 -to enet_rx_er
115set_location_assignment PIN_E10 -to enet_tx_clk
116set_location_assignment PIN_R5 -to enet_tx_d[0]
117set_location_assignment PIN_P5 -to enet_tx_d[1]
118set_location_assignment PIN_W1 -to enet_tx_d[2]
119set_location_assignment PIN_W2 -to enet_tx_d[3]
120set_location_assignment PIN_R4 -to enet_tx_en
121set_location_assignment PIN_P4 -to enet_tx_er
122set_location_assignment PIN_R9 -to enet_led_link100
123set_location_assignment PIN_B2 -to qspi_clk
124set_location_assignment PIN_C6 -to qspi_io[0]
125set_location_assignment PIN_C3 -to qspi_io[1]
126set_location_assignment PIN_C5 -to qspi_io[2]
127set_location_assignment PIN_B1 -to qspi_io[3]
128set_location_assignment PIN_C2 -to qspi_csn
129set_location_assignment PIN_C22 -to mem_a[13]
130set_location_assignment PIN_J14 -to mem_a[12]
131set_location_assignment PIN_E20 -to mem_a[11]
132set_location_assignment PIN_Y20 -to mem_a[10]
133set_location_assignment PIN_E22 -to mem_a[9]
134set_location_assignment PIN_D22 -to mem_a[8]
135set_location_assignment PIN_B20 -to mem_a[7]
136set_location_assignment PIN_C20 -to mem_a[4]
137set_location_assignment PIN_A21 -to mem_a[2]
138set_location_assignment PIN_D19 -to mem_a[1]
139set_location_assignment PIN_E21 -to mem_a[6]
140set_location_assignment PIN_F19 -to mem_a[5]
141set_location_assignment PIN_U20 -to mem_a[3]
142set_location_assignment PIN_V20 -to mem_a[0]
143set_location_assignment PIN_W22 -to mem_ba[2]
144set_location_assignment PIN_N18 -to mem_ba[1]
145set_location_assignment PIN_V22 -to mem_ba[0]
146set_location_assignment PIN_U19 -to mem_cas_n[0]
147set_location_assignment PIN_D18 -to mem_ck[0]
148set_location_assignment PIN_E18 -to mem_ck_n[0]
149set_location_assignment PIN_W20 -to mem_cke[0]
150set_location_assignment PIN_Y22 -to mem_cs_n[0]
151set_location_assignment PIN_J15 -to mem_dm[0]
152set_location_assignment PIN_K19 -to mem_dq[7]
153set_location_assignment PIN_H20 -to mem_dq[6]
154set_location_assignment PIN_J20 -to mem_dq[5]
155set_location_assignment PIN_H19 -to mem_dq[4]
156set_location_assignment PIN_K18 -to mem_dq[3]
157set_location_assignment PIN_H18 -to mem_dq[2]
158set_location_assignment PIN_K20 -to mem_dq[1]
159set_location_assignment PIN_J18 -to mem_dq[0]
160set_location_assignment PIN_K14 -to mem_dqs[0]
161set_location_assignment PIN_W19 -to mem_odt[0]
162set_location_assignment PIN_V18 -to mem_ras_n[0]
163set_location_assignment PIN_B22 -to mem_reset_n
164set_location_assignment PIN_Y21 -to mem_we_n[0]
165set_location_assignment PIN_L20 -to mem_dq[8]
166set_location_assignment PIN_M18 -to mem_dq[9]
167set_location_assignment PIN_M20 -to mem_dq[10]
168set_location_assignment PIN_M14 -to mem_dq[11]
169set_location_assignment PIN_L18 -to mem_dq[12]
170set_location_assignment PIN_M15 -to mem_dq[13]
171set_location_assignment PIN_L19 -to mem_dq[14]
172set_location_assignment PIN_N20 -to mem_dq[15]
173set_location_assignment PIN_L14 -to mem_dqs[1]
174set_location_assignment PIN_N19 -to mem_dm[1]
175set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
176set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
177set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
178set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
179set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
180set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to clk_ddr3_100_p
181set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_50_max10
182set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_25_max10
183set_instance_assignment -name IO_STANDARD LVDS -to clk_lvds_125_p
184set_instance_assignment -name IO_STANDARD "2.5 V" -to clk_10_adc
185set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_resetn
186set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[0]
187set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[1]
188set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[2]
189set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[3]
190set_instance_assignment -name IO_STANDARD "1.5 V" -to user_led[4]
191set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[0]
192set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[1]
193set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[2]
194set_instance_assignment -name IO_STANDARD "1.5 V" -to user_pb[3]
195set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[0]
196set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[1]
197set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[2]
198set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[3]
199set_instance_assignment -name IO_STANDARD "1.5 V" -to user_dipsw[4]
200set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[0]
201set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_led[2]
202set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to user_pb[1]
203set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_gtx_clk
204set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_intn
205set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_resetn
206set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_clk
207set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_col
208set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_crs
209set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[0]
210set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[1]
211set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[2]
212set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_d[3]
213set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_dv
214set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_rx_er
215set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_tx_clk
216set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[0]
217set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[1]
218set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[2]
219set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_d[3]
220set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_en
221set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_tx_er
222set_instance_assignment -name IO_STANDARD "2.5 V" -to enet_led_link100
223set_instance_assignment -name GLOBAL_SIGNAL_CLKCTRL_LOCATION CLKCTRL_G2 -to enet_rx_clk
224set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_clk
225set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[0]
226set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[1]
227set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[2]
228set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_io[3]
229set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to qspi_csn
230set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
231set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
232set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
233set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
234set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
235set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
236set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
237set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
238set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
239set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
240set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
241set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
242set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
243set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
244set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
245set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
246set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_dqs[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
247set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
248set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_dqs_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
249set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
250set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_ck[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
251set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_ck[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
252set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_ck_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
253set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_ck_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
254set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
255set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
256set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
257set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
258set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
259set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
260set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
261set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
262set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
263set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
264set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
265set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
266set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_a[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
267set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_ba[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
268set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_ba[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
269set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_ba[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
270set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_cs_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
271set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_we_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
272set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_ras_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
273set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_cas_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
274set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_cke[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
275set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_odt[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
276set_instance_assignment -name IO_STANDARD 1.5V -to mem_reset_n -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
277set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dm[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
278set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dm[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
279set_instance_assignment -name CKN_CK_PAIR ON -from mem_ck_n[0] -to mem_ck[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
280set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
281set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
282set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
283set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
284set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
285set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
286set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
287set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
288set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dm[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
289set_instance_assignment -name DM_PIN ON -to mem_dm[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
290set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
291set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
292set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
293set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
294set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
295set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
296set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
297set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
298set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dm[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
299set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
300set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
301set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
302set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
303set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
304set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
305set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
306set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
307set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[3] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
308set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[4] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
309set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[5] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
310set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[6] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
311set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[7] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
312set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
313set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
314set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
315set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
316set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[2] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
317set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cs_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
318set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_we_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
319set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ras_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
320set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cas_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
321set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cke[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
322set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_odt[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
323set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_reset_n -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
324set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ck[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
325set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ck_n[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
326set_instance_assignment -name GLOBAL_SIGNAL OFF -to q_sys_inst|mem_if_ddr3_emif_0|p0|umemphy|ureset|phy_reset_n -tag __q_sys_mem_if_ddr3_emif_0_p0
327set_instance_assignment -name GLOBAL_SIGNAL OFF -to q_sys_inst|mem_if_ddr3_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __q_sys_mem_if_ddr3_emif_0_p0
328set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to q_sys_inst|mem_if_ddr3_emif_0 -tag __q_sys_mem_if_ddr3_emif_0_p0
329set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[13] -tag __q_sys_mem_if_ddr3_emif_0_p0
330set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[13] -tag __q_sys_mem_if_ddr3_emif_0_p0
331set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[4]
332set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[1]
333set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[7]
334set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to mem_a[2]
335set_instance_assignment -name GLOBAL_SIGNAL OFF -to "ghrd_system:ghrd_system_inst|ghrd_system_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|ghrd_system_mem_if_ddr3_emif_0_p0:p0|ghrd_system_mem_if_ddr3_emif_0_p0_memphy_m10:umemphy|ghrd_system_mem_if_ddr3_emif_0_p0_reset_m10:ureset|phy_reset_n"
336set_instance_assignment -name GLOBAL_SIGNAL OFF -to "ghrd_system:ghrd_system_inst|ghrd_system_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|ghrd_system_mem_if_ddr3_emif_0_p0:p0|ghrd_system_mem_if_ddr3_emif_0_p0_memphy_m10:umemphy|ghrd_system_mem_if_ddr3_emif_0_p0_read_datapath_m10:uread_datapath|rdata_per_dq_group[0].reset_n_fifo_wraddress[0]"
337set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_dqs[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
338set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
339set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL" -to mem_dqs_n[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
340set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs_n[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
341set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
342set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs_n[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
343set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
344set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
345set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
346set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
347set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[13] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
348set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[14] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
349set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[15] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
350set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
351set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
352set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
353set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
354set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
355set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[13] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
356set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[14] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
357set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[15] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
358set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dq[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
359set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
360set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
361set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
362set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
363set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
364set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[13] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
365set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[14] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
366set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[15] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
367set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[9] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
368set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[10] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
369set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[11] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
370set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[12] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
371set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[13] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
372set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[14] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
373set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[15] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
374set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dq[8] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
375set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[1] -to mem_dm[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
376set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_dm[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
377set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dm[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
378set_instance_assignment -name DM_PIN ON -to mem_dm[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
379set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dm[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
380set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_system_inst|mem_if_ddr3_emif_0|p0|umemphy|ureset|phy_reset_n -tag __ghrd_system_mem_if_ddr3_emif_0_p0
381set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_system_inst|mem_if_ddr3_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __ghrd_system_mem_if_ddr3_emif_0_p0
382set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_system_inst|mem_if_ddr3_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -tag __ghrd_system_mem_if_ddr3_emif_0_p0
383set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to ghrd_system_inst|mem_if_ddr3_emif_0 -tag __ghrd_system_mem_if_ddr3_emif_0_p0
384set_instance_assignment -name GLOBAL_SIGNAL OFF -to "dut_example_if0:if0|dut_example_if0_p0:p0|dut_example_if0_p0_ghrd_system_mem_if_ddr3_emif_0_p0_m10:umemphy|dut_example_if0_p0_dqdqs_pads_m10:dq_ddio[*].ubidir_dq_dqs|altera_gpio_lite:dq_ddio_io|altgpio_one_bit:gpio_one_bit.i_loop[*].altgpio_bit_i|fr_clock"
385set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_10m50daf484c6ges_inst|mem_if_ddr3_emif_0|p0|umemphy|ureset|phy_reset_n -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
386set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_10m50daf484c6ges_inst|mem_if_ddr3_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
387set_instance_assignment -name GLOBAL_SIGNAL OFF -to ghrd_10m50daf484c6ges_inst|mem_if_ddr3_emif_0|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
388set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to ghrd_10m50daf484c6ges_inst|mem_if_ddr3_emif_0 -tag __ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0
389set_instance_assignment -name GLOBAL_SIGNAL OFF -to "dut_example_if0:if0|dut_example_if0_p0:p0|dut_example_if0_p0_ghrd_10m50daf484c6ges_mem_if_ddr3_emif_0_p0_m10:umemphy|dut_example_if0_p0_dqdqs_pads_m10:dq_ddio[*].ubidir_dq_dqs|altera_gpio_lite:dq_ddio_io|altgpio_one_bit:gpio_one_bit.i_loop[*].altgpio_bit_i|fr_clock"
390set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
391set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
392set_location_assignment PIN_M9 -to clk_50
393set_location_assignment PIN_D9 -to fpga_reset_n
394set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
395set_global_assignment -name VERILOG_FILE ghrd_10m50da_top.v
396set_global_assignment -name QIP_FILE ghrd_10m50da/synthesis/ghrd_10m50da.qip
397set_global_assignment -name SDC_FILE ghrd_timing.sdc
398
399set_location_assignment PIN_A10 -to i2c_scl
400set_location_assignment PIN_B15 -to i2c_sda
401set_location_assignment PIN_B7 -to spi_sclk
402set_location_assignment PIN_A6 -to spi_miso
403set_location_assignment PIN_C8 -to spi_mosi
404set_location_assignment PIN_C7 -to spi_ssn
405set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_miso
406set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_mosi
407set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_sclk
408set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to spi_ssn
409set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to fpga_reset_n
410set_global_assignment -name USE_SIGNALTAP_FILE output_files/uart.stp
411set_global_assignment -name SIGNALTAP_FILE output_files/uart.stp
412set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top