1 /*
2 * Copyright (c) 2019 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /**
8 * @file
9 * @brief System/hardware module for STM32H7 CM7 processor
10 */
11
12 #include <zephyr/kernel.h>
13 #include <zephyr/device.h>
14 #include <zephyr/init.h>
15 #include <zephyr/cache.h>
16 #include <soc.h>
17 #include <stm32_ll_bus.h>
18 #include <stm32_ll_pwr.h>
19 #include <stm32_ll_rcc.h>
20 #include <stm32_ll_system.h>
21 #include "stm32_hsem.h"
22
23 #include <cmsis_core.h>
24
25 #if defined(CONFIG_STM32H7_DUAL_CORE)
stm32h7_m4_wakeup(void)26 static int stm32h7_m4_wakeup(void)
27 {
28
29 /* HW semaphore and SysCfg Clock enable */
30 LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM);
31 LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG);
32
33 if (READ_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4)) {
34 /* Cortex-M4 is waiting for end of system initialization made by
35 * Cortex-M7. This initialization is now finished,
36 * then Cortex-M7 takes HSEM so that CM4 can continue running.
37 */
38 LL_HSEM_1StepLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID);
39 } else if (IS_ENABLED(CONFIG_STM32H7_BOOT_M4_AT_INIT)) {
40 /* CM4 is not started at boot, start it now */
41 LL_RCC_ForceCM4Boot();
42 }
43
44 return 0;
45 }
46 #endif /* CONFIG_STM32H7_DUAL_CORE */
47
48 /**
49 * @brief Perform basic hardware initialization at boot.
50 *
51 * This needs to be run from the very beginning.
52 * So the init priority has to be 0 (zero).
53 *
54 * @return 0
55 */
stm32h7_init(void)56 static int stm32h7_init(void)
57 {
58 sys_cache_instr_enable();
59 sys_cache_data_enable();
60
61 /* Update CMSIS SystemCoreClock variable (HCLK) */
62 /* At reset, system core clock is set to 64 MHz from HSI */
63 SystemCoreClock = 64000000;
64
65 /* Power Configuration */
66 #if !defined(SMPS) && \
67 (defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS) || \
68 defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO) || \
69 defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO) || \
70 defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || \
71 defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || \
72 defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT) || \
73 defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT))
74 #error Unsupported configuration: Selected SoC do not support SMPS
75 #endif
76 #if defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
77 LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
78 #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
79 LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_LDO);
80 #elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO)
81 LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_LDO);
82 #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO)
83 LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO);
84 #elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO)
85 LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO);
86 #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT)
87 LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT);
88 #elif defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT)
89 LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT);
90 #elif defined(CONFIG_POWER_SUPPLY_EXTERNAL_SOURCE)
91 LL_PWR_ConfigSupply(LL_PWR_EXTERNAL_SOURCE_SUPPLY);
92 #else
93 LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
94 #endif
95 LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
96 while (LL_PWR_IsActiveFlag_VOS() == 0) {
97 }
98
99 /* Errata ES0392 Rev 8:
100 * 2.2.9: Reading from AXI SRAM may lead to data read corruption
101 * Workaround: Set the READ_ISS_OVERRIDE bit in the AXI_TARG7_FN_MOD
102 * register.
103 * Applicable only to RevY (REV_ID 0x1003)
104 */
105 if (LL_DBGMCU_GetRevisionID() == 0x1003) {
106 MODIFY_REG(GPV->AXI_TARG7_FN_MOD, 0x1, 0x1);
107 }
108
109 return 0;
110 }
111
112 SYS_INIT(stm32h7_init, PRE_KERNEL_1, 0);
113
114
115 #if defined(CONFIG_STM32H7_DUAL_CORE)
116 /* Unlock M4 once system configuration has been done */
117 SYS_INIT(stm32h7_m4_wakeup, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY);
118 #endif /* CONFIG_STM32H7_DUAL_CORE */
119
