1# Nuvoton Cortex-M4 Embedded Controller
2
3# Copyright (c) 2020 Nuvoton Technology Corporation.
4# SPDX-License-Identifier: Apache-2.0
5
6config SOC_FAMILY_NPCX
7	bool
8
9if SOC_FAMILY_NPCX
10config SOC_FAMILY
11	string
12	default "nuvoton_npcx"
13
14menuconfig NPCX_HEADER
15	bool "The output binary with NPCX binary header"
16	help
17	  On NPCX series chip, the NPCX ROM code loads firmware image from flash
18	  to RAM by the firmware binary header setting. Enable this to invoke
19	  the 'ecst' which generates the NPCX firmware header.
20
21if NPCX_HEADER
22
23config NPCX_IMAGE_OUTPUT_BIN
24	bool "Build npcx binary in BIN format"
25	default y
26	help
27	  Build a "raw" binary zephyr/zephyr.npcx.bin in the build directory.
28	  The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
29
30config NPCX_IMAGE_OUTPUT_HEX
31	bool "Build npcx binary in HEX format"
32	depends on NPCX_IMAGE_OUTPUT_BIN
33	help
34	  Build an HEX binary zephyr/zephyr.npcx.hex in the build directory.
35	  This is generated from the npcx BIN image.
36	  The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
37
38config NPCX_HEADER_CHIP
39	string
40	default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC
41	default "npcx7m7" if SOC_NPCX7M7FC
42	default "npcx9m3" if SOC_NPCX9M3F
43	default "npcx9m6" if SOC_NPCX9M6F
44	default "npcx9m7" if SOC_NPCX9M7F
45	default "npcx9mfp" if SOC_NPCX9MFP
46	default "npcx4m3" if SOC_NPCX4M3F
47	default "npcx4m8" if SOC_NPCX4M8F
48
49choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE
50	prompt "Clock rate to use for SPI flash"
51	default NPCX_HEADER_SPI_MAX_CLOCK_20
52	help
53	  This selects the max clock rate that will be used for loading firmware
54	  binary from flash to RAM.
55
56config NPCX_HEADER_SPI_MAX_CLOCK_20
57	bool "SPI flash max clock rate of 20 MHz"
58
59config NPCX_HEADER_SPI_MAX_CLOCK_25
60	bool "SPI flash max clock rate of 25 MHz"
61
62config NPCX_HEADER_SPI_MAX_CLOCK_33
63	bool "SPI flash max clock rate of 33 MHz"
64	depends on !SOC_SERIES_NPCX9
65
66config NPCX_HEADER_SPI_MAX_CLOCK_40
67	bool "SPI flash max clock rate of 40 MHz"
68
69config NPCX_HEADER_SPI_MAX_CLOCK_50
70	bool "SPI flash max clock rate of 50 MHz"
71endchoice
72
73config NPCX_HEADER_SPI_MAX_CLOCK
74	int
75	default 20 if NPCX_HEADER_SPI_MAX_CLOCK_20
76	default 25 if NPCX_HEADER_SPI_MAX_CLOCK_25
77	default 33 if NPCX_HEADER_SPI_MAX_CLOCK_33
78	default 40 if NPCX_HEADER_SPI_MAX_CLOCK_40
79	default 50 if NPCX_HEADER_SPI_MAX_CLOCK_50
80
81choice NPCX_HEADER_SPI_READ_MODE_CHOICE
82	prompt "Reading mode used by the SPI flash"
83	default NPCX_HEADER_SPI_READ_MODE_NORMAL
84	help
85	  This sets the reading mode that can be used by the SPI flash.
86	  Reading modes supported are normal, fast, dual, and quad.
87
88config NPCX_HEADER_SPI_READ_MODE_NORMAL
89	bool "SPI flash operates with normal reading mode"
90
91config NPCX_HEADER_SPI_READ_MODE_FAST
92	bool "SPI flash operates with fast reading mode"
93
94config NPCX_HEADER_SPI_READ_MODE_DUAL
95	bool "SPI flash operates with dual reading mode"
96
97config NPCX_HEADER_SPI_READ_MODE_QUAD
98	bool "SPI flash operates with quad reading mode"
99endchoice
100
101config NPCX_HEADER_SPI_READ_MODE
102	string
103	default "normal" if NPCX_HEADER_SPI_READ_MODE_NORMAL
104	default "fast" if NPCX_HEADER_SPI_READ_MODE_FAST
105	default "dual" if NPCX_HEADER_SPI_READ_MODE_DUAL
106	default "quad" if NPCX_HEADER_SPI_READ_MODE_QUAD
107
108choice NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_CHOICE
109	prompt "Core clock to SPI flash clock ratio"
110	default NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
111	help
112	  This sets the clock ratio (core clock / SPI clock)
113
114config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
115	bool "NPCX SPI clock ratio 1"
116	help
117	  The SPI flash clock has the same frequency as the core clock.
118
119config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
120	bool "NPCX SPI clock ratio 2"
121	help
122	  The core clock frequency is twice the flash clock frequency.
123endchoice
124
125config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO
126	int
127	default 1 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
128	default 2 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
129
130config NPCX_HEADER_ENABLE_HEADER_CRC
131	bool "Header crc check"
132	help
133	  When enabled, the header will be verified at boot using a crc
134	  checksum.
135
136config NPCX_HEADER_ENABLE_FIRMWARE_CRC
137	bool "Firmware image crc check"
138	help
139	  When enabled, the firmware image will be verified at boot using a
140	  crc checksum.
141
142choice NPCX_HEADER_FLASH_SIZE_CHOICE
143	prompt "Flash size"
144	default NPCX_HEADER_FLASH_SIZE_0P5M_1M if SOC_SERIES_NPCX7 || \
145						  SOC_SERIES_NPCX9
146	default NPCX_HEADER_FLASH_SIZE_16M
147	help
148	  This sets the SPI flash size.
149
150config NPCX_HEADER_FLASH_SIZE_0P5M_1M
151	bool "SPI flash size 0.5M or 1M Bytes"
152	help
153	  The SPI flash size is 0.5M or 1M Bytes.
154
155config NPCX_HEADER_FLASH_SIZE_2M
156	bool "SPI flash size 2M Bytes"
157	help
158	  The SPI flash size is 2M Bytes.
159
160config NPCX_HEADER_FLASH_SIZE_4M
161	bool "SPI flash size 4M Bytes"
162	help
163	  The SPI flash size is 4M Bytes.
164
165config NPCX_HEADER_FLASH_SIZE_8M
166	bool "SPI flash size 8M Bytes"
167	help
168	  The SPI flash size is 8M Bytes.
169
170config NPCX_HEADER_FLASH_SIZE_16M
171	bool "SPI flash size 16M Bytes"
172	help
173	  The SPI flash size is 16M Bytes.
174endchoice
175
176config NPCX_HEADER_FLASH_SIZE
177	int
178	default 1 if NPCX_HEADER_FLASH_SIZE_0P5M_1M
179	default 2 if NPCX_HEADER_FLASH_SIZE_2M
180	default 4 if NPCX_HEADER_FLASH_SIZE_4M
181	default 8 if NPCX_HEADER_FLASH_SIZE_8M
182	default 16 if NPCX_HEADER_FLASH_SIZE_16M
183
184endif # NPCX_HEADER
185
186# Select SoC Part No. and configuration options
187source "soc/arm/nuvoton_npcx/*/Kconfig.soc"
188
189config NPCX_PM_TRACE
190	bool "Trace System Power Management in NPCX family"
191	depends on PM
192	help
193	  Internal config to enable runtime power management traces.
194
195endif # SOC_FAMILY_NPCX
196