1# Nordic Semiconductor nRF53 MCU line
2
3# Copyright (c) 2019 Nordic Semiconductor ASA
4# SPDX-License-Identifier: Apache-2.0
5
6if SOC_SERIES_NRF53X
7config SOC_NRF5340_CPUAPP
8	bool
9	select CPU_HAS_NRF_IDAU
10	select CPU_HAS_FPU
11	select ARMV8_M_DSP
12	select HAS_POWEROFF
13	select SOC_COMPATIBLE_NRF5340_CPUAPP
14	imply SOC_NRF53_RTC_PRETICK
15	imply SOC_NRF53_ANOMALY_168_WORKAROUND
16
17config SOC_NRF5340_CPUNET
18	bool
19	select SOC_COMPATIBLE_NRF5340_CPUNET
20	imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
21	imply SOC_NRF53_RTC_PRETICK if !WDT_NRFX
22	imply SOC_NRF53_ANOMALY_168_WORKAROUND
23
24choice
25	prompt "nRF53x MCU Selection"
26
27config SOC_NRF5340_CPUAPP_QKAA
28	bool "NRF5340_CPUAPP_QKAA"
29	select SOC_NRF5340_CPUAPP
30
31config SOC_NRF5340_CPUNET_QKAA
32	bool "NRF5340_CPUNET_QKAA"
33	select SOC_NRF5340_CPUNET
34
35endchoice
36
37config SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
38	bool "Workaround for nRF5340 anomaly 160"
39	imply SOC_NRF53_ANOMALY_160_WORKAROUND
40	help
41	  Indicates that the workaround for the anomaly 160 that affects
42	  the nRF5340 SoC should be applied.
43	  This option is enabled by default for the Application MCU when
44	  DC/DC mode is enabled for the VREGMAIN or VREGRADIO regulator
45	  and always for the Network MCU.
46	  If this option is enabled, but the workaround cannot be applied,
47	  because the system clock is disabled, a related cmake warning is
48	  issued.
49
50config SOC_NRF53_ANOMALY_160_WORKAROUND
51	bool
52	depends on SYS_CLOCK_EXISTS
53	select ARM_ON_ENTER_CPU_IDLE_HOOK
54
55config SOC_NRF53_RTC_PRETICK
56	bool "Pre-tick workaround for nRF5340 anomaly 165"
57	depends on (SYS_CLOCK_EXISTS && SOC_NRF5340_CPUNET) || SOC_NRF5340_CPUAPP
58	select NRFX_DPPI
59	select ARM_ON_ENTER_CPU_IDLE_HOOK if SOC_NRF5340_CPUNET
60	select ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK if SOC_NRF5340_CPUNET
61	help
62	  Indicates that the pre-tick workaround for the anomaly 165 that affects
63	  the nRF5340 SoC should be applied. The workaround applies to wake ups caused
64	  by EVENTS_COMPARE and EVENTS_OVRFLW on RTC0 and RTC1 for which interrupts are
65	  enabled through INTENSET register. The case when these events are generated
66	  by EVTEN but without interrupts enabled through INTENSET is not handled.
67	  The EVENTS_TICK event is not handled.
68
69if SOC_NRF53_RTC_PRETICK
70
71config SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET
72	int "IPC 0 channel for RTC pretick"
73	range 0 15
74	default 10
75
76config SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET
77	int "IPC 1 channel for RTC pretick"
78	range 0 15
79	default 11
80
81endif
82
83config SOC_NRF53_ANOMALY_168_WORKAROUND
84	bool "Workaround for nRF5340 anomaly 168"
85	select ARM_ON_EXIT_CPU_IDLE
86	help
87	  Indicates that the workaround for the anomaly 168 that affects
88	  the nRF5340 SoC should be applied.
89	  The workaround involves execution of 8 NOP instructions when the CPU
90	  exist its idle state (when the WFI/WFE instruction returns) and it is
91	  enabled by default for both the application and network core.
92
93config SOC_NRF53_ANOMALY_168_WORKAROUND_FOR_EXECUTION_FROM_RAM
94	bool "Extend the workaround to execution at 128 MHz from RAM"
95	depends on SOC_NRF53_ANOMALY_168_WORKAROUND && SOC_NRF5340_CPUAPP
96	help
97	  Indicates that the anomaly 168 workaround is to be extended to cover
98	  also a specific case when the WFI/WFE instruction is executed at 128
99	  MHz from RAM. Then, 26 instead of 8 NOP instructions needs to be
100	  executed after WFI/WFE. This extension is not enabled by default.
101
102if SOC_NRF5340_CPUAPP
103
104config SOC_DCDC_NRF53X_APP
105	bool
106	imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
107	help
108	  Enable nRF53 series System on Chip Application MCU DC/DC converter.
109
110config SOC_DCDC_NRF53X_NET
111	bool
112	imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
113	help
114	  Enable nRF53 series System on Chip Network MCU DC/DC converter.
115
116config SOC_DCDC_NRF53X_HV
117	bool
118	help
119	  Enable nRF53 series System on Chip High Voltage DC/DC converter.
120
121config NRF_SPU_FLASH_REGION_SIZE
122	hex
123	default 0x4000
124	help
125	  FLASH region size for the NRF_SPU peripheral
126
127config NRF_SPU_RAM_REGION_SIZE
128	hex
129	default 0x2000
130	help
131	  RAM region size for the NRF_SPU peripheral
132
133config SOC_NRF_GPIO_FORWARDER_FOR_NRF5340
134	bool
135	depends on NRF_SOC_SECURE_SUPPORTED
136	help
137	  hidden option for including the nRF GPIO pin forwarding
138
139if !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM
140
141config SOC_ENABLE_LFXO
142	bool "LFXO"
143	default y
144	help
145	  Enable the low-frequency oscillator (LFXO) functionality on XL1 and
146	  XL2 pins.
147	  This option must be enabled if either application or network core is
148	  to use the LFXO. Otherwise, XL1 and XL2 pins will behave as regular
149	  GPIOs.
150
151choice SOC_LFXO_LOAD_CAPACITANCE
152	prompt "LFXO load capacitance"
153	depends on SOC_ENABLE_LFXO
154	default SOC_LFXO_CAP_INT_7PF
155
156config SOC_LFXO_CAP_EXTERNAL
157	bool "Use external load capacitors"
158
159config SOC_LFXO_CAP_INT_6PF
160	bool "6 pF internal load capacitance"
161
162config SOC_LFXO_CAP_INT_7PF
163	bool "7 pF internal load capacitance"
164
165config SOC_LFXO_CAP_INT_9PF
166	bool "9 pF internal load capacitance"
167
168endchoice
169
170choice SOC_HFXO_LOAD_CAPACITANCE
171	prompt "HFXO load capacitance"
172	default SOC_HFXO_CAP_DEFAULT
173
174config SOC_HFXO_CAP_DEFAULT
175	bool "SoC default"
176	help
177	  When this option is used, the SoC initialization routine does not
178	  touch the XOSC32MCAPS register value, so the default setting for
179	  the SoC is in effect. Please note that this may not necessarily be
180	  the reset value (0) for the register, as the register can be set
181	  during the device trimming in the SystemInit() function.
182
183config SOC_HFXO_CAP_EXTERNAL
184	bool "Use external load capacitors"
185
186config SOC_HFXO_CAP_INTERNAL
187	bool "Use internal load capacitors"
188	depends on NRF_SOC_SECURE_SUPPORTED
189
190endchoice
191
192config SOC_HFXO_CAP_INT_VALUE_X2
193	int "Doubled value of HFXO internal load capacitors (in pF)"
194	depends on SOC_HFXO_CAP_INTERNAL
195	range 14 40
196	help
197	  Internal capacitors ranging from 7.0 pF to 20.0 pF in 0.5 pF steps
198	  can be enabled on pins XC1 and XC2. This option specifies doubled
199	  capacitance value for the two capacitors. Set it to 14 to get 7.0 pF
200	  for each capacitor, 15 to get 7.5 pF, and so on.
201
202endif # !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM
203
204endif # SOC_NRF5340_CPUAPP
205
206
207config NRF_ENABLE_CACHE
208	bool "Cache"
209	depends on (SOC_NRF5340_CPUAPP && (!TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM)) \
210			|| SOC_NRF5340_CPUNET
211	default y
212	help
213	  Instruction and Data cache is available on nRF5340 CPUAPP
214	  (Application MCU). It may only be accessed by Secure code.
215
216	  Instruction cache only (I-Cache) is available in nRF5340
217	  CPUNET (Network MCU).
218
219config BUILD_WITH_TFM
220	# TF-M nRF53 platform enables the cache unconditionally.
221	select NRF_ENABLE_CACHE if SOC_NRF5340_CPUAPP
222
223rsource "Kconfig.sync_rtc"
224
225endif # SOC_SERIES_NRF53X
226