1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <zephyr/sys/__assert.h> 8 #include <zephyr/device.h> 9 #include <zephyr/init.h> 10 #include <soc.h> 11 #include <zephyr/kernel.h> 12 #include <zephyr/arch/cpu.h> 13 #include <cmsis_core.h> 14 15 /* Enable SWD and ETM debug interface and pins. 16 * NOTE: ETM TRACE pins exposed on MEC172x EVB J30 12,14,16,18,20. 17 */ configure_debug_interface(void)18static void configure_debug_interface(void) 19 { 20 struct ecs_regs *ecs = (struct ecs_regs *)(DT_REG_ADDR(DT_NODELABEL(ecs))); 21 22 #ifdef CONFIG_SOC_MEC172X_DEBUG_DISABLED 23 ecs->ETM_CTRL = 0; 24 ecs->DEBUG_CTRL = 0; 25 #elif defined(CONFIG_SOC_MEC172X_DEBUG_WITHOUT_TRACING) 26 ecs->ETM_CTRL = 0; 27 ecs->DEBUG_CTRL = (MCHP_ECS_DCTRL_DBG_EN | MCHP_ECS_DCTRL_MODE_SWD); 28 #elif defined(CONFIG_SOC_MEC172X_DEBUG_AND_TRACING) 29 30 #if defined(CONFIG_SOC_MEC172X_DEBUG_AND_ETM_TRACING) 31 ecs->ETM_CTRL = 1u; 32 ecs->DEBUG_CTRL = (MCHP_ECS_DCTRL_DBG_EN | MCHP_ECS_DCTRL_MODE_SWD); 33 #elif defined(CONFIG_SOC_MEC172X_DEBUG_AND_SWV_TRACING) 34 ecs->ETM_CTRL = 0; 35 ecs->DEBUG_CTRL = (MCHP_ECS_DCTRL_DBG_EN | MCHP_ECS_DCTRL_MODE_SWD_SWV); 36 #endif /* CONFIG_SOC_MEC172X_DEBUG_AND_ETM_TRACING */ 37 38 #endif /* CONFIG_SOC_MEC172X_DEBUG_DISABLED */ 39 } 40 soc_init(void)41static int soc_init(void) 42 { 43 44 configure_debug_interface(); 45 46 return 0; 47 } 48 49 SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); 50
