1/* 2 * Copyright (c) 2022 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <xtensa/xtensa.dtsi> 8#include <mem.h> 9 10/ { 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu0: cpu@0 { 16 device_type = "cpu"; 17 compatible = "cdns,tensilica-xtensa-lx7"; 18 reg = <0>; 19 cpu-power-states = <&d0i3 &d3>; 20 i-cache-line-size = <64>; 21 d-cache-line-size = <64>; 22 }; 23 24 cpu1: cpu@1 { 25 device_type = "cpu"; 26 compatible = "cdns,tensilica-xtensa-lx7"; 27 reg = <1>; 28 cpu-power-states = <&d0i3 &d3>; 29 }; 30 31 cpu2: cpu@2 { 32 device_type = "cpu"; 33 compatible = "cdns,tensilica-xtensa-lx7"; 34 reg = <2>; 35 cpu-power-states = <&d0i3 &d3>; 36 }; 37 38 power-states { 39 d0i3: idle { 40 compatible = "zephyr,power-state"; 41 power-state-name = "runtime-idle"; 42 min-residency-us = <200>; 43 exit-latency-us = <100>; 44 }; 45 /* PM_STATE_SOFT_OFF can be entered only by calling pm_state_force. 46 * The procedure is triggered by IPC from the HOST (SET_DX). 47 */ 48 d3: off { 49 compatible = "zephyr,power-state"; 50 power-state-name = "soft-off"; 51 min-residency-us = <2147483647>; 52 exit-latency-us = <0>; 53 }; 54 }; 55 }; 56 57 sram0: memory@a0020000 { 58 device_type = "memory"; 59 compatible = "mmio-sram"; 60 reg = <0xa0020000 DT_SIZE_K(2816)>; 61 }; 62 63 sram0virtual: virtualmemory@a0020000 { 64 device_type = "memory"; 65 compatible = "mmio-sram"; 66 reg = <0xa0020000 DT_SIZE_K(8192)>; 67 }; 68 69 sram1: memory@a0000000 { 70 device_type = "memory"; 71 compatible = "mmio-sram"; 72 reg = <0xa0000000 DT_SIZE_K(64)>; 73 }; 74 75 sysclk: system-clock { 76 compatible = "fixed-clock"; 77 clock-frequency = <38400000>; 78 #clock-cells = <0>; 79 }; 80 81 clkctl: clkctl { 82 compatible = "intel,adsp-shim-clkctl"; 83 adsp-clkctl-clk-wovcro = <0>; 84 adsp-clkctl-clk-ipll = <1>; 85 adsp-clkctl-freq-enc = <0xc 0x4>; 86 adsp-clkctl-freq-mask = <0x0 0x0>; 87 adsp-clkctl-freq-default = <1>; 88 adsp-clkctl-freq-lowest = <0>; 89 wovcro-supported; 90 }; 91 92 audioclk: audio-clock { 93 compatible = "fixed-clock"; 94 clock-frequency = <24576000>; 95 #clock-cells = <0>; 96 }; 97 98 pllclk: pll-clock { 99 compatible = "fixed-clock"; 100 clock-frequency = <96000000>; 101 #clock-cells = <0>; 102 }; 103 104 IMR1: memory@A1000000 { 105 compatible = "intel,adsp-imr"; 106 reg = <0xA1000000 DT_SIZE_M(16)>; 107 block-size = <0x1000>; 108 zephyr,memory-region = "IMR1"; 109 }; 110 111 soc { 112 core_intc: core_intc@0 { 113 compatible = "cdns,xtensa-core-intc"; 114 reg = <0x00 0x400>; 115 interrupt-controller; 116 #interrupt-cells = <3>; 117 }; 118 119 dmic0: dmic0@10000 { 120 compatible = "intel,dai-dmic"; 121 reg = <0x10000 0x8000>; 122 shim = <0xC000>; 123 fifo = <0x0008>; 124 interrupts = <0x08 0 0>; 125 interrupt-parent = <&ace_intc>; 126 power-domain = <&hub_ulp_domain>; 127 }; 128 129 dmic1: dmic1@10000 { 130 compatible = "intel,dai-dmic"; 131 reg = <0x10000 0x8000>; 132 shim = <0xC000>; 133 fifo = <0x0108>; 134 interrupts = <0x09 0 0>; 135 interrupt-parent = <&ace_intc>; 136 power-domain = <&hub_ulp_domain>; 137 }; 138 139 /* 140 * FIXME this is modeling individual alh channels/instances 141 * with node labels, which has problems. A better representation 142 * is discussed here: 143 * 144 * https://github.com/zephyrproject-rtos/zephyr/pull/50287#discussion_r974591009 145 * 146 * The hardware actually supports 16 ALH streams/FIFOs. Below description does 147 * not fully represent hardware capabilities and is expected to be modified. 148 */ 149 alh0: alh0@24400 { 150 compatible = "intel,alh-dai"; 151 reg = <0x00024400 0x00024600>; 152 status = "okay"; 153 }; 154 155 alh1: alh1@24400 { 156 compatible = "intel,alh-dai"; 157 reg = <0x00024400 0x00024600>; 158 status = "okay"; 159 }; 160 161 alh2: alh2@24400 { 162 compatible = "intel,alh-dai"; 163 reg = <0x00024400 0x00024600>; 164 status = "okay"; 165 }; 166 167 alh3: alh3@24400 { 168 compatible = "intel,alh-dai"; 169 reg = <0x00024400 0x00024600>; 170 status = "okay"; 171 }; 172 173 alh4: alh4@24400 { 174 compatible = "intel,alh-dai"; 175 reg = <0x00024400 0x00024600>; 176 status = "okay"; 177 }; 178 179 alh5: alh5@24400 { 180 compatible = "intel,alh-dai"; 181 reg = <0x00024400 0x00024600>; 182 status = "okay"; 183 }; 184 185 alh6: alh6@24400 { 186 compatible = "intel,alh-dai"; 187 reg = <0x00024400 0x00024600>; 188 status = "okay"; 189 }; 190 191 alh7: alh7@24400 { 192 compatible = "intel,alh-dai"; 193 reg = <0x00024400 0x00024600>; 194 status = "okay"; 195 }; 196 197 alh8: alh8@24400 { 198 compatible = "intel,alh-dai"; 199 reg = <0x00024400 0x00024600>; 200 status = "okay"; 201 }; 202 203 alh9: alh9@24400 { 204 compatible = "intel,alh-dai"; 205 reg = <0x00024400 0x00024600>; 206 status = "okay"; 207 }; 208 209 alh10: alh10@24400 { 210 compatible = "intel,alh-dai"; 211 reg = <0x00024400 0x00024600>; 212 status = "okay"; 213 }; 214 215 alh11: alh11@24400 { 216 compatible = "intel,alh-dai"; 217 reg = <0x00024400 0x00024600>; 218 status = "okay"; 219 }; 220 221 alh12: alh12@24400 { 222 compatible = "intel,alh-dai"; 223 reg = <0x00024400 0x00024600>; 224 status = "okay"; 225 }; 226 227 alh13: alh13@24400 { 228 compatible = "intel,alh-dai"; 229 reg = <0x00024400 0x00024600>; 230 status = "okay"; 231 }; 232 233 alh14: alh14@24400 { 234 compatible = "intel,alh-dai"; 235 reg = <0x00024400 0x00024600>; 236 status = "okay"; 237 }; 238 239 alh15: alh15@24400 { 240 compatible = "intel,alh-dai"; 241 reg = <0x00024400 0x00024600>; 242 status = "okay"; 243 }; 244 245 ssp0: ssp@28000 { 246 compatible = "intel,ssp-dai"; 247 #address-cells = <1>; 248 #size-cells = <0>; 249 reg = <0x00028000 0x1000 250 0x00079C00 0x200>; 251 interrupts = <0x00 0 0>; 252 interrupt-parent = <&ace_intc>; 253 dmas = <&lpgpdma0 2 254 &lpgpdma0 3>; 255 dma-names = "tx", "rx"; 256 power-domain = <&io0_domain>; 257 status = "okay"; 258 }; 259 260 sspbase: ssp_base@28800 { 261 compatible = "intel,ssp-sspbase"; 262 reg = <0x28800 0x1000>; 263 }; 264 265 ssp1: ssp@29000 { 266 compatible = "intel,ssp-dai"; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 reg = <0x00029000 0x1000 270 0x00079C00 0x200>; 271 interrupts = <0x01 0 0>; 272 interrupt-parent = <&ace_intc>; 273 dmas = <&lpgpdma0 4 274 &lpgpdma0 5>; 275 dma-names = "tx", "rx"; 276 power-domain = <&io0_domain>; 277 status = "okay"; 278 }; 279 280 ssp2: ssp@2a000 { 281 compatible = "intel,ssp-dai"; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 reg = <0x0002a000 0x1000 285 0x00079C00 0x200>; 286 interrupts = <0x02 0 0>; 287 interrupt-parent = <&ace_intc>; 288 dmas = <&lpgpdma0 6 289 &lpgpdma0 7>; 290 dma-names = "tx", "rx"; 291 power-domain = <&io0_domain>; 292 status = "okay"; 293 }; 294 295 ssp3: ssp@2b000 { 296 compatible = "intel,ssp-dai"; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 reg = <0x0002b000 0x1000 300 0x00079C00 0x200>; 301 interrupts = <0x03 0 0>; 302 interrupt-parent = <&ace_intc>; 303 dmas = <&lpgpdma0 8 304 &lpgpdma0 9>; 305 dma-names = "tx", "rx"; 306 power-domain = <&io0_domain>; 307 status = "okay"; 308 }; 309 310 ssp4: ssp@2c000 { 311 compatible = "intel,ssp-dai"; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 reg = <0x0002c000 0x1000 315 0x00079C00 0x200>; 316 interrupts = <0x04 0 0>; 317 interrupt-parent = <&ace_intc>; 318 dmas = <&lpgpdma0 10 319 &lpgpdma0 11>; 320 dma-names = "tx", "rx"; 321 power-domain = <&io0_domain>; 322 status = "okay"; 323 }; 324 325 ssp5: ssp@2d000 { 326 compatible = "intel,ssp-dai"; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 reg = <0x0002d000 0x1000 330 0x00079C00 0x200>; 331 interrupts = <0x04 0 0>; 332 interrupt-parent = <&ace_intc>; 333 dmas = <&lpgpdma0 12 334 &lpgpdma0 13>; 335 dma-names = "tx", "rx"; 336 power-domain = <&io0_domain>; 337 status = "okay"; 338 }; 339 340 mem_window0: mem_window@70200 { 341 compatible = "intel,adsp-mem-window"; 342 reg = <0x70200 0x8>; 343 offset = <0x4000>; 344 memory = <&sram0>; 345 initialize; 346 read-only; 347 }; 348 349 mem_window1: mem_window@70208 { 350 compatible = "intel,adsp-mem-window"; 351 reg = <0x70208 0x8>; 352 memory = <&sram0>; 353 }; 354 355 mem_window2: mem_window@70210 { 356 compatible = "intel,adsp-mem-window"; 357 reg = <0x70210 0x8>; 358 memory = <&sram0>; 359 }; 360 361 mem_window3: mem_window@70218 { 362 compatible = "intel,adsp-mem-window"; 363 reg = <0x70218 0x8>; 364 memory = <&sram0>; 365 read-only; 366 }; 367 368 adsp_idc: ace_idc@70400 { 369 compatible = "intel,adsp-idc"; 370 reg = <0x70400 0x0400>; 371 interrupts = <24 0 0>; 372 interrupt-parent = <&ace_intc>; 373 }; 374 375 dfpmcch: dfpmcch@71ac0 { 376 compatible = "intel,adsp-dfpmcch"; 377 reg = <0x00071ac0 0x40>; 378 }; 379 380 dfpmccu: dfpmccu@71b00 { 381 compatible = "intel,adsp-dfpmccu"; 382 reg = <0x71b00 0x100>; 383 384 hub_ulp_domain: hub_ulp_domain { 385 compatible = "intel,adsp-power-domain"; 386 bit-position = <15>; 387 }; 388 hub_hp_domain: hub_hp_domain { 389 compatible = "intel,adsp-power-domain"; 390 bit-position = <6>; 391 }; 392 io0_domain: io0_domain { 393 compatible = "intel,adsp-power-domain"; 394 bit-position = <8>; 395 }; 396 io1_domain: io1_domain { 397 compatible = "intel,adsp-power-domain"; 398 bit-position = <9>; 399 }; 400 io2_domain: io2_domain { 401 compatible = "intel,adsp-power-domain"; 402 bit-position = <10>; 403 }; 404 io3_domain: io3_domain { 405 compatible = "intel,adsp-power-domain"; 406 bit-position = <11>; 407 }; 408 hst_domain: hst_domain { 409 compatible = "intel,adsp-power-domain"; 410 bit-position = <4>; 411 }; 412 ml0_domain: ml0_domain { 413 compatible = "intel,adsp-power-domain"; 414 bit-position = <12>; 415 }; 416 ml1_domain: ml1_domain { 417 compatible = "intel,adsp-power-domain"; 418 bit-position = <13>; 419 }; 420 }; 421 422 ace_comm_widget: ace_comm_widget@71c00 { 423 compatible = "intel,adsp-communication-widget"; 424 reg = <0x00071c00 0x100>; 425 interrupts = <0x19 0 0>; 426 interrupt-parent = <&ace_intc>; 427 status = "okay"; 428 }; 429 430 shim: shim@71f00 { 431 compatible = "intel,adsp-shim"; 432 reg = <0x71f00 0x100>; 433 }; 434 435 tts: tts@72000 { 436 compatible = "intel,adsp-tts"; 437 reg = <0x72000 0x70>; 438 status = "okay"; 439 }; 440 441 ace_rtc_counter: ace_rtc_counter@72008 { 442 compatible = "intel,ace-rtc-counter"; 443 reg = <0x72008 0x0064>; 444 }; 445 446 ace_timestamp: ace_timestamp@72040 { 447 compatible = "intel,ace-timestamp"; 448 reg = <0x72040 0x0032>; 449 }; 450 451 ace_art_counter: ace_art_counter@72058 { 452 compatible = "intel,ace-art-counter"; 453 reg = <0x72058 0x0064>; 454 }; 455 456 hda_link_out: dma@72400 { 457 compatible = "intel,adsp-hda-link-out"; 458 #dma-cells = <1>; 459 reg = <0x00072400 0x20>; 460 dma-channels = <9>; 461 dma-buf-addr-alignment = <128>; 462 dma-buf-size-alignment = <32>; 463 dma-copy-alignment = <32>; 464 power-domain = <&hst_domain>; 465 status = "okay"; 466 }; 467 468 hda_link_in: dma@72600 { 469 compatible = "intel,adsp-hda-link-in"; 470 #dma-cells = <1>; 471 reg = <0x00072600 0x20>; 472 dma-channels = <10>; 473 dma-buf-addr-alignment = <128>; 474 dma-buf-size-alignment = <32>; 475 dma-copy-alignment = <32>; 476 power-domain = <&hst_domain>; 477 status = "okay"; 478 }; 479 480 hda_host_out: dma@72800 { 481 compatible = "intel,adsp-hda-host-out"; 482 #dma-cells = <1>; 483 reg = <0x00072800 0x40>; 484 dma-channels = <9>; 485 dma-buf-addr-alignment = <128>; 486 dma-buf-size-alignment = <32>; 487 dma-copy-alignment = <32>; 488 power-domain = <&hst_domain>; 489 interrupts = <13 0 0>; 490 interrupt-parent = <&ace_intc>; 491 status = "okay"; 492 }; 493 494 hda_host_in: dma@72c00 { 495 compatible = "intel,adsp-hda-host-in"; 496 #dma-cells = <1>; 497 reg = <0x00072c00 0x40>; 498 dma-channels = <10>; 499 dma-buf-addr-alignment = <128>; 500 dma-buf-size-alignment = <32>; 501 dma-copy-alignment = <32>; 502 power-domain = <&hst_domain>; 503 interrupts = <12 0 0>; 504 interrupt-parent = <&ace_intc>; 505 status = "okay"; 506 }; 507 508 adsp_host_ipc: ace_host_ipc@73000 { 509 compatible = "intel,adsp-host-ipc"; 510 status = "okay"; 511 reg = <0x73000 0x30>; 512 interrupts = <0 0 0>; 513 interrupt-parent = <&ace_intc>; 514 }; 515 516 /* This is actually an array of per-core designware 517 * controllers, but the special setup and extra 518 * masking layer makes it easier for MTL to handle 519 * this internally. 520 */ 521 ace_intc: ace_intc@7ac00 { 522 compatible = "intel,ace-intc"; 523 reg = <0x7ac00 0xc00>; 524 interrupt-controller; 525 #interrupt-cells = <3>; 526 interrupts = <4 0 0>; 527 num-irqs = <28>; 528 interrupt-parent = <&core_intc>; 529 }; 530 531 lpgpdma0: dma@7c000 { 532 compatible = "intel,adsp-gpdma"; 533 #dma-cells = <1>; 534 reg = <0x0007c000 0x1000>; 535 shim = <0x0007c800 0x1000>; 536 interrupts = <17 0 0>; 537 interrupt-parent = <&ace_intc>; 538 dma-buf-size-alignment = <4>; 539 dma-copy-alignment = <4>; 540 status = "okay"; 541 power-domain = <&hub_ulp_domain>; 542 zephyr,pm-device-runtime-auto; 543 }; 544 545 lpgpdma1: dma@7d000 { 546 compatible = "intel,adsp-gpdma"; 547 #dma-cells = <1>; 548 reg = <0x0007d000 0x1000>; 549 shim = <0x0007d800 0x1000>; 550 interrupts = <0x20 0 0>; 551 interrupt-parent = <&core_intc>; 552 dma-buf-size-alignment = <4>; 553 dma-copy-alignment = <4>; 554 status = "okay"; 555 power-domain = <&io0_domain>; 556 zephyr,pm-device-runtime-auto; 557 }; 558 559 lpgpdma2: dma@7e000 { 560 compatible = "intel,adsp-gpdma"; 561 #dma-cells = <1>; 562 reg = <0x0007e000 0x1000>; 563 shim = <0x0007e800 0x1000>; 564 interrupts = <0x25 0 0>; 565 interrupt-parent = <&core_intc>; 566 dma-buf-size-alignment = <4>; 567 dma-copy-alignment = <4>; 568 power-domain = <&io0_domain>; 569 status = "okay"; 570 zephyr,pm-device-runtime-auto; 571 }; 572 573 sha: adsp-sha@17df00 { 574 compatible = "intel,adsp-sha"; 575 reg = <0x17df00 0xd0>; 576 }; 577 578 tlb: tlb@17e000 { 579 compatible = "intel,adsp-mtl-tlb"; 580 reg = <0x17e000 0x1000>; 581 paddr-size = <12>; 582 exec-bit-idx = <14>; 583 write-bit-idx= <15>; 584 }; 585 586 timer: timer { 587 compatible = "intel,adsp-timer"; 588 syscon = <&tts>; 589 }; 590 }; 591 592 hdas { 593 #address-cells = <1>; 594 #size-cells = <0>; 595 596 hda0: hda@0 { 597 compatible = "intel,hda-dai"; 598 status = "okay"; 599 reg = <0>; 600 }; 601 hda1: hda@1 { 602 compatible = "intel,hda-dai"; 603 status = "okay"; 604 reg = <1>; 605 }; 606 hda2: hda@2 { 607 compatible = "intel,hda-dai"; 608 status = "okay"; 609 reg = <2>; 610 }; 611 hda3: hda@3 { 612 compatible = "intel,hda-dai"; 613 status = "okay"; 614 reg = <3>; 615 }; 616 hda4: hda@4 { 617 compatible = "intel,hda-dai"; 618 status = "okay"; 619 reg = <4>; 620 }; 621 hda5: hda@5 { 622 compatible = "intel,hda-dai"; 623 status = "okay"; 624 reg = <5>; 625 }; 626 hda6: hda@6 { 627 compatible = "intel,hda-dai"; 628 status = "okay"; 629 reg = <6>; 630 }; 631 hda7: hda@7 { 632 compatible = "intel,hda-dai"; 633 status = "okay"; 634 reg = <7>; 635 }; 636 hda8: hda@8 { 637 compatible = "intel,hda-dai"; 638 status = "okay"; 639 reg = <8>; 640 }; 641 hda9: hda@9 { 642 compatible = "intel,hda-dai"; 643 status = "okay"; 644 reg = <9>; 645 }; 646 hda10: hda@a { 647 compatible = "intel,hda-dai"; 648 status = "okay"; 649 reg = <0x0a>; 650 }; 651 hda11: hda@b { 652 compatible = "intel,hda-dai"; 653 status = "okay"; 654 reg = <0x0b>; 655 }; 656 hda12: hda@c { 657 compatible = "intel,hda-dai"; 658 status = "okay"; 659 reg = <0x0c>; 660 }; 661 hda13: hda@d { 662 compatible = "intel,hda-dai"; 663 status = "okay"; 664 reg = <0x0d>; 665 }; 666 hda14: hda@e { 667 compatible = "intel,hda-dai"; 668 status = "okay"; 669 reg = <0x0e>; 670 }; 671 hda15: hda@f { 672 compatible = "intel,hda-dai"; 673 status = "okay"; 674 reg = <0x0f>; 675 }; 676 hda16: hda@10 { 677 compatible = "intel,hda-dai"; 678 status = "okay"; 679 reg = <0x10>; 680 }; 681 hda17: hda@11 { 682 compatible = "intel,hda-dai"; 683 status = "okay"; 684 reg = <0x11>; 685 }; 686 hda18: hda@12 { 687 compatible = "intel,hda-dai"; 688 status = "okay"; 689 reg = <0x12>; 690 }; 691 }; 692}; 693
