1/* 2 * Copyright (c) 2020 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include "skeleton.dtsi" 8#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h> 9#include <zephyr/dt-bindings/i2c/i2c.h> 10#include <zephyr/dt-bindings/pcie/pcie.h> 11 12/ { 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 device_type = "cpu"; 19 compatible = "intel,elkhart-lake"; 20 d-cache-line-size = <64>; 21 reg = <0>; 22 }; 23 24 }; 25 26 dram0: memory@0 { 27 device_type = "memory"; 28 reg = <0x0 DT_DRAM_SIZE>; 29 }; 30 31 ibecc: ibecc { 32 compatible = "intel,ibecc"; 33 status = "okay"; 34 }; 35 36 intc: ioapic@fec00000 { 37 compatible = "intel,ioapic"; 38 #address-cells = <1>; 39 #interrupt-cells = <3>; 40 reg = <0xfec00000 0x1000>; 41 interrupt-controller; 42 }; 43 44 intc_loapic: loapic@fee00000 { 45 compatible = "intel,loapic"; 46 reg = <0xfee00000 0x1000>; 47 interrupt-controller; 48 #interrupt-cells = <3>; 49 #address-cells = <1>; 50 }; 51 52 pcie0: pcie0 { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 compatible = "pcie-controller"; 56 acpi-hid = "PNP0A08"; 57 ranges; 58 59 ptm_root0: ptm_root0 { 60 compatible = "ptm-root"; 61 62 vendor-id = <0x8086>; 63 device-id = <0x4b38>; 64 65 status = "okay"; 66 }; 67 68 uart0: uart0 { 69 compatible = "ns16550"; 70 71 vendor-id = <0x8086>; 72 device-id = <0x4b28>; 73 74 reg-shift = <2>; 75 clock-frequency = <1843200>; 76 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 77 interrupt-parent = <&intc>; 78 status = "okay"; 79 current-speed = <115200>; 80 }; 81 82 uart1: uart1 { 83 compatible = "ns16550"; 84 85 vendor-id = <0x8086>; 86 device-id = <0x4b29>; 87 88 reg-shift = <2>; 89 clock-frequency = <1843200>; 90 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 91 interrupt-parent = <&intc>; 92 93 status = "okay"; 94 current-speed = <115200>; 95 }; 96 97 uart2: uart2 { 98 compatible = "ns16550"; 99 100 vendor-id = <0x8086>; 101 device-id = <0x4b4d>; 102 103 reg-shift = <2>; 104 clock-frequency = <1843200>; 105 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 106 interrupt-parent = <&intc>; 107 108 status = "okay"; 109 current-speed = <115200>; 110 }; 111 112 uart_pse_0: uart_pse_0 { 113 compatible = "ns16550"; 114 115 vendor-id = <0x8086>; 116 device-id = <0x4b96>; 117 118 reg-shift = <2>; 119 clock-frequency = <1843200>; 120 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 121 interrupt-parent = <&intc>; 122 123 status = "disabled"; 124 current-speed = <115200>; 125 }; 126 127 uart_pse_1: uart_pse_1 { 128 compatible = "ns16550"; 129 130 vendor-id = <0x8086>; 131 device-id = <0x4b97>; 132 133 reg-shift = <2>; 134 clock-frequency = <1843200>; 135 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 136 interrupt-parent = <&intc>; 137 138 status = "disabled"; 139 current-speed = <115200>; 140 }; 141 142 uart_pse_2: uart_pse_2 { 143 compatible = "ns16550"; 144 145 vendor-id = <0x8086>; 146 device-id = <0x4b98>; 147 148 reg-shift = <2>; 149 clock-frequency = <1843200>; 150 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 151 interrupt-parent = <&intc>; 152 153 status = "disabled"; 154 current-speed = <115200>; 155 }; 156 157 uart_pse_3: uart_pse_3 { 158 compatible = "ns16550"; 159 160 vendor-id = <0x8086>; 161 device-id = <0x4b99>; 162 163 reg-shift = <2>; 164 clock-frequency = <1843200>; 165 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 166 interrupt-parent = <&intc>; 167 168 status = "disabled"; 169 current-speed = <115200>; 170 }; 171 172 uart_pse_4: uart_pse_4 { 173 compatible = "ns16550"; 174 175 vendor-id = <0x8086>; 176 device-id = <0x4b9a>; 177 178 reg-shift = <2>; 179 clock-frequency = <1843200>; 180 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 181 interrupt-parent = <&intc>; 182 183 status = "disabled"; 184 current-speed = <115200>; 185 }; 186 187 uart_pse_5: uart_pse_5 { 188 compatible = "ns16550"; 189 190 vendor-id = <0x8086>; 191 device-id = <0x4b9b>; 192 193 reg-shift = <2>; 194 clock-frequency = <1843200>; 195 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 196 interrupt-parent = <&intc>; 197 198 status = "disabled"; 199 current-speed = <115200>; 200 }; 201 202 smbus0: smbus0 { 203 compatible = "intel,pch-smbus"; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 vendor-id = <0x8086>; 207 device-id = <0x4b23>; 208 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 209 interrupt-parent = <&intc>; 210 211 status = "okay"; 212 }; 213 214 i2c0: i2c0 { 215 compatible = "snps,designware-i2c"; 216 clock-frequency = <I2C_BITRATE_STANDARD>; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 vendor-id = <0x8086>; 220 device-id = <0x4b78>; 221 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 222 interrupt-parent = <&intc>; 223 224 status = "okay"; 225 }; 226 227 i2c1: i2c1 { 228 compatible = "snps,designware-i2c"; 229 clock-frequency = <I2C_BITRATE_STANDARD>; 230 #address-cells = <1>; 231 #size-cells = <0>; 232 vendor-id = <0x8086>; 233 device-id = <0x4b79>; 234 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 235 interrupt-parent = <&intc>; 236 237 status = "okay"; 238 }; 239 240 i2c2: i2c2 { 241 compatible = "snps,designware-i2c"; 242 clock-frequency = <I2C_BITRATE_STANDARD>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 vendor-id = <0x8086>; 246 device-id = <0x4b7a>; 247 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 248 interrupt-parent = <&intc>; 249 250 status = "okay"; 251 }; 252 253 i2c3: i2c3 { 254 compatible = "snps,designware-i2c"; 255 clock-frequency = <I2C_BITRATE_STANDARD>; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 vendor-id = <0x8086>; 259 device-id = <0x4b7b>; 260 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 261 interrupt-parent = <&intc>; 262 263 status = "okay"; 264 }; 265 266 i2c4: i2c4 { 267 compatible = "snps,designware-i2c"; 268 clock-frequency = <I2C_BITRATE_STANDARD>; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 vendor-id = <0x8086>; 272 device-id = <0x4b4b>; 273 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 274 interrupt-parent = <&intc>; 275 276 status = "okay"; 277 }; 278 279 i2c5: i2c5 { 280 compatible = "snps,designware-i2c"; 281 clock-frequency = <I2C_BITRATE_STANDARD>; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 vendor-id = <0x8086>; 285 device-id = <0x4b4c>; 286 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 287 interrupt-parent = <&intc>; 288 289 status = "okay"; 290 }; 291 292 i2c6: i2c6 { 293 compatible = "snps,designware-i2c"; 294 clock-frequency = <I2C_BITRATE_STANDARD>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 vendor-id = <0x8086>; 298 device-id = <0x4b44>; 299 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 300 interrupt-parent = <&intc>; 301 302 status = "okay"; 303 }; 304 305 i2c7: i2c7 { 306 compatible = "snps,designware-i2c"; 307 clock-frequency = <I2C_BITRATE_STANDARD>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 vendor-id = <0x8086>; 311 device-id = <0x4b45>; 312 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 313 interrupt-parent = <&intc>; 314 315 status = "okay"; 316 }; 317 318 i2c_pse_0: i2c_pse_0 { 319 compatible = "snps,designware-i2c"; 320 clock-frequency = <I2C_BITRATE_STANDARD>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 vendor-id = <0x8086>; 324 device-id = <0x4bb9>; 325 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 326 interrupt-parent = <&intc>; 327 328 status = "okay"; 329 }; 330 331 i2c_pse_1: i2c_pse_1 { 332 compatible = "snps,designware-i2c"; 333 clock-frequency = <I2C_BITRATE_STANDARD>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 vendor-id = <0x8086>; 337 device-id = <0x4bba>; 338 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 339 interrupt-parent = <&intc>; 340 341 status = "okay"; 342 }; 343 344 i2c_pse_2: i2c_pse_2 { 345 compatible = "snps,designware-i2c"; 346 clock-frequency = <I2C_BITRATE_STANDARD>; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 vendor-id = <0x8086>; 350 device-id = <0x4bbb>; 351 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 352 interrupt-parent = <&intc>; 353 354 status = "okay"; 355 }; 356 357 i2c_pse_3: i2c_pse_3 { 358 compatible = "snps,designware-i2c"; 359 clock-frequency = <I2C_BITRATE_STANDARD>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 vendor-id = <0x8086>; 363 device-id = <0x4bbc>; 364 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 365 interrupt-parent = <&intc>; 366 367 status = "okay"; 368 }; 369 370 i2c_pse_4: i2c_pse_4 { 371 compatible = "snps,designware-i2c"; 372 clock-frequency = <I2C_BITRATE_STANDARD>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 vendor-id = <0x8086>; 376 device-id = <0x4bbd>; 377 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 378 interrupt-parent = <&intc>; 379 380 status = "okay"; 381 }; 382 383 i2c_pse_5: i2c_pse_5 { 384 compatible = "snps,designware-i2c"; 385 clock-frequency = <I2C_BITRATE_STANDARD>; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 vendor-id = <0x8086>; 389 device-id = <0x4bbe>; 390 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 391 interrupt-parent = <&intc>; 392 393 status = "okay"; 394 }; 395 396 i2c_pse_6: i2c_pse_6 { 397 compatible = "snps,designware-i2c"; 398 clock-frequency = <I2C_BITRATE_STANDARD>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 vendor-id = <0x8086>; 402 device-id = <0x4bbf>; 403 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 404 interrupt-parent = <&intc>; 405 406 status = "okay"; 407 }; 408 }; 409 410 soc { 411 #address-cells = <1>; 412 #size-cells = <1>; 413 compatible = "simple-bus"; 414 ranges; 415 416 vtd: vtd@fed91000 { 417 compatible = "intel,vt-d"; 418 419 reg = <0xfed91000 0x1000>; 420 421 status = "okay"; 422 }; 423 424 425 uart1_fixed: uart@fe040000 { 426 compatible = "ns16550"; 427 428 reg = <0xfe040000 0x1000>; 429 reg-shift = <0>; 430 431 clock-frequency = <1843200>; 432 interrupts = <3 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 433 interrupt-parent = <&intc>; 434 435 status = "disabled"; 436 current-speed = <115200>; 437 }; 438 439 uart2_fixed: uart@fe042000 { 440 compatible = "ns16550"; 441 442 reg = <0xfe042000 0x1000>; 443 reg-shift = <0>; 444 445 clock-frequency = <1843200>; 446 interrupts = <4 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 447 interrupt-parent = <&intc>; 448 449 status = "disabled"; 450 current-speed = <115200>; 451 }; 452 453 gpio_0_b: gpio@fd6e0700 { 454 compatible = "intel,gpio"; 455 reg = <0xfd6e0700 0x1000>; 456 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 457 interrupt-parent = <&intc>; 458 459 group-index = <0x0>; 460 gpio-controller; 461 #gpio-cells = <2>; 462 463 ngpios = <24>; 464 pin-offset = <0>; 465 466 status = "okay"; 467 }; 468 469 gpio_0_t: gpio@fd6e08a0 { 470 compatible = "intel,gpio"; 471 reg = <0xfd6e08a0 0x1000>; 472 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 473 interrupt-parent = <&intc>; 474 475 group-index = <0x1>; 476 gpio-controller; 477 #gpio-cells = <2>; 478 479 ngpios = <16>; 480 pin-offset = <26>; 481 482 status = "okay"; 483 }; 484 485 gpio_0_g: gpio@fd6e09a0 { 486 compatible = "intel,gpio"; 487 reg = <0xfd6e09a0 0x1000>; 488 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 489 interrupt-parent = <&intc>; 490 491 group-index = <0x2>; 492 gpio-controller; 493 #gpio-cells = <2>; 494 495 ngpios = <24>; 496 pin-offset = <42>; 497 498 status = "okay"; 499 }; 500 501 gpio_1_v: gpio@fd6d0700 { 502 compatible = "intel,gpio"; 503 reg = <0xfd6d0700 0x1000>; 504 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 505 interrupt-parent = <&intc>; 506 507 group-index = <0x0>; 508 gpio-controller; 509 #gpio-cells = <2>; 510 511 ngpios = <16>; 512 pin-offset = <0>; 513 514 status = "okay"; 515 }; 516 517 gpio_1_h: gpio@fd6d0800 { 518 compatible = "intel,gpio"; 519 reg = <0xfd6d0800 0x1000>; 520 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 521 interrupt-parent = <&intc>; 522 523 group-index = <0x1>; 524 gpio-controller; 525 #gpio-cells = <2>; 526 527 ngpios = <24>; 528 pin-offset = <16>; 529 530 status = "okay"; 531 }; 532 533 gpio_1_d: gpio@fd6d0980 { 534 compatible = "intel,gpio"; 535 reg = <0xfd6d0980 0x1000>; 536 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 537 interrupt-parent = <&intc>; 538 539 group-index = <0x2>; 540 gpio-controller; 541 #gpio-cells = <2>; 542 543 ngpios = <20>; 544 pin-offset = <40>; 545 546 status = "okay"; 547 }; 548 549 gpio_1_u: gpio@fd6d0ad0 { 550 compatible = "intel,gpio"; 551 reg = <0xfd6d0ad0 0x1000>; 552 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 553 interrupt-parent = <&intc>; 554 555 group-index = <0x3>; 556 gpio-controller; 557 #gpio-cells = <2>; 558 559 ngpios = <20>; 560 pin-offset = <61>; 561 562 status = "okay"; 563 }; 564 565 gpio_1_vG: gpio@fd6d0c50 { 566 compatible = "intel,gpio"; 567 reg = <0xfd6d0c50 0x1000>; 568 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 569 interrupt-parent = <&intc>; 570 571 group-index = <0x4>; 572 gpio-controller; 573 #gpio-cells = <2>; 574 575 ngpios = <28>; 576 pin-offset = <85>; 577 578 status = "okay"; 579 }; 580 581 gpio_3_s: gpio@fd6b0810 { 582 compatible = "intel,gpio"; 583 reg = <0xfd6b0810 0x1000>; 584 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 585 interrupt-parent = <&intc>; 586 587 group-index = <0x1>; 588 gpio-controller; 589 #gpio-cells = <2>; 590 591 ngpios = <2>; 592 pin-offset = <17>; 593 594 status = "okay"; 595 }; 596 597 gpio_3_a: gpio@fd6b0830 { 598 compatible = "intel,gpio"; 599 reg = <0xfd6b0830 0x1000>; 600 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 601 interrupt-parent = <&intc>; 602 603 group-index = <0x2>; 604 gpio-controller; 605 #gpio-cells = <2>; 606 607 ngpios = <24>; 608 pin-offset = <25>; 609 610 status = "okay"; 611 }; 612 613 gpio_3_vG: gpio@fd6b09b0 { 614 compatible = "intel,gpio"; 615 reg = <0xfd6b09b0 0x1000>; 616 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 617 interrupt-parent = <&intc>; 618 619 group-index = <0x3>; 620 gpio-controller; 621 #gpio-cells = <2>; 622 623 ngpios = <4>; 624 pin-offset = <49>; 625 626 status = "okay"; 627 }; 628 629 gpio_4_c: gpio@fd6a0700 { 630 compatible = "intel,gpio"; 631 reg = <0xfd6a0700 0x1000>; 632 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 633 interrupt-parent = <&intc>; 634 635 group-index = <0x0>; 636 gpio-controller; 637 #gpio-cells = <2>; 638 639 ngpios = <24>; 640 pin-offset = <0>; 641 642 status = "okay"; 643 }; 644 645 gpio_4_f: gpio@fd6a0880 { 646 compatible = "intel,gpio"; 647 reg = <0xfd6a0880 0x1000>; 648 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 649 interrupt-parent = <&intc>; 650 651 group-index = <0x1>; 652 gpio-controller; 653 #gpio-cells = <2>; 654 655 ngpios = <24>; 656 pin-offset = <24>; 657 658 status = "okay"; 659 }; 660 661 gpio_4_e: gpio@fd6a0a70 { 662 compatible = "intel,gpio"; 663 reg = <0xfd6a0a70 0x1000>; 664 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 665 interrupt-parent = <&intc>; 666 667 group-index = <0x3>; 668 gpio-controller; 669 #gpio-cells = <2>; 670 671 ngpios = <24>; 672 pin-offset = <57>; 673 674 status = "okay"; 675 }; 676 677 gpio_5_r: gpio@fd690700 { 678 compatible = "intel,gpio"; 679 reg = <0xfd690700 0x1000>; 680 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 681 interrupt-parent = <&intc>; 682 683 group-index = <0x0>; 684 gpio-controller; 685 #gpio-cells = <2>; 686 687 ngpios = <8>; 688 pin-offset = <0>; 689 690 status = "okay"; 691 }; 692 693 hpet: hpet@fed00000 { 694 compatible = "intel,hpet"; 695 reg = <0xfed00000 0x400>; 696 interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>; 697 interrupt-parent = <&intc>; 698 699 status = "okay"; 700 }; 701 702 tco_wdt: tco_wdt@400 { 703 compatible = "intel,tco-wdt"; 704 reg = <0x0400 0x20>; 705 706 status = "disabled"; 707 }; 708 709 rtc: counter: rtc@70 { 710 compatible = "motorola,mc146818"; 711 reg = <0x70 0x0D 0x71 0x0D>; 712 interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>; 713 interrupt-parent = <&intc>; 714 alarms-count = <1>; 715 716 status = "okay"; 717 }; 718 719 }; 720}; 721
