1/*
2 * Copyright 2018 Foundries.io Ltd
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6#include <zephyr/dt-bindings/interrupt-controller/openisa-intmux.h>
7#include <zephyr/dt-bindings/gpio/gpio.h>
8#include <zephyr/dt-bindings/i2c/i2c.h>
9#include <zephyr/dt-bindings/pwm/pwm.h>
10
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14
15	chosen {
16		zephyr,entropy = &trng;
17		zephyr,flash-controller = &ftfe;
18	};
19
20	cpus {
21		#address-cells = <1>;
22		#size-cells = <0>;
23		cpu@0 {
24			device_type = "cpu";
25			compatible = "openisa,ri5cy", "riscv";
26			riscv,isa = "rv32ima_zicsr_zifencei";
27			reg = <0>;
28		};
29
30		cpu@1 {
31			device_type = "cpu";
32			compatible = "openisa,zero-ri5cy", "riscv";
33			riscv,isa = "rv32ima_zicsr_zifencei";
34			reg = <1>;
35		};
36	};
37
38	m4_dtcm: memory@20000000 {
39		compatible = "mmio-sram";
40		reg = <0x20000000 0x30000>;
41	};
42
43	m0_tcm: memory@9000000 {
44		compatible = "mmio-sram";
45		reg = <0x09000000 0x20000>;
46	};
47
48	/* Dummy pinctrl node, filled with pin mux options at board level */
49	pinctrl: pinctrl {
50		compatible = "openisa,rv32m1-pinctrl";
51		status = "okay";
52	};
53
54	soc {
55		#address-cells = <1>;
56		#size-cells = <1>;
57		compatible = "simple-bus";
58		ranges;
59
60		pcc0: clock-controller@4002b000 {
61			compatible = "openisa,rv32m1-pcc";
62			reg = <0x4002b000 0x200>;
63			#clock-cells = <1>;
64		};
65
66		pcc1: clock-controller@41027000 {
67			compatible = "openisa,rv32m1-pcc";
68			reg = <0x41027000 0x200>;
69			#clock-cells = <1>;
70		};
71
72		event0: interrupt-controller@e0041000 {
73			compatible = "openisa,rv32m1-event-unit";
74			#address-cells = <0>;
75			#interrupt-cells = <1>;
76			interrupt-controller;
77			reg = <0xe0041000 0x88>;
78		};
79
80		event1: interrupt-controller@4101f000 {
81			compatible = "openisa,rv32m1-event-unit";
82			#address-cells = <0>;
83			#interrupt-cells = <1>;
84			interrupt-controller;
85			reg = <0x4101f000 0x88>;
86		};
87
88		intmux0: intmux@4004f000 {
89			compatible = "openisa,rv32m1-intmux";
90			reg = <0x4004f000 0x200>;
91			clocks = <&pcc0 0x13c>;
92			status = "disabled";
93			#address-cells = <1>;
94			#size-cells = <1>;
95
96			ranges = <0x0 0x4004f000 0x200>;
97
98			intmux0_ch0: interrupt-controller@0 {
99				compatible = "openisa,rv32m1-intmux-ch";
100				#address-cells = <0>;
101				#interrupt-cells = <1>;
102				interrupt-controller;
103				interrupts = <INTMUX_CH0_IRQ>;
104				reg = <0x0 0x40>;
105				status = "disabled";
106			};
107
108			intmux0_ch1: interrupt-controller@40 {
109				compatible = "openisa,rv32m1-intmux-ch";
110				#address-cells = <0>;
111				#interrupt-cells = <1>;
112				interrupt-controller;
113				interrupts = <INTMUX_CH1_IRQ>;
114				reg = <0x40 0x40>;
115				status = "disabled";
116			};
117
118			intmux0_ch2: interrupt-controller@80 {
119				compatible = "openisa,rv32m1-intmux-ch";
120				#address-cells = <0>;
121				#interrupt-cells = <1>;
122				interrupt-controller;
123				interrupts = <INTMUX_CH2_IRQ>;
124				reg = <0x80 0x40>;
125				status = "disabled";
126			};
127
128			intmux0_ch3: interrupt-controller@c0 {
129				compatible = "openisa,rv32m1-intmux-ch";
130				#address-cells = <0>;
131				#interrupt-cells = <1>;
132				interrupt-controller;
133				interrupts = <INTMUX_CH3_IRQ>;
134				reg = <0xc0 0x40>;
135				status = "disabled";
136			};
137
138			intmux0_ch4: interrupt-controller@100 {
139				compatible = "openisa,rv32m1-intmux-ch";
140				#address-cells = <0>;
141				#interrupt-cells = <1>;
142				interrupt-controller;
143				interrupts = <INTMUX_CH4_IRQ>;
144				reg = <0x100 0x40>;
145				status = "disabled";
146			};
147
148			intmux0_ch5: interrupt-controller@140 {
149				compatible = "openisa,rv32m1-intmux-ch";
150				#address-cells = <0>;
151				#interrupt-cells = <1>;
152				interrupt-controller;
153				interrupts = <INTMUX_CH5_IRQ>;
154				reg = <0x140 0x40>;
155				status = "disabled";
156			};
157
158			intmux0_ch6: interrupt-controller@180 {
159				compatible = "openisa,rv32m1-intmux-ch";
160				#address-cells = <0>;
161				#interrupt-cells = <1>;
162				interrupt-controller;
163				interrupts = <INTMUX_CH6_IRQ>;
164				reg = <0x180 0x40>;
165				status = "disabled";
166			};
167
168			intmux0_ch7: interrupt-controller@1c0 {
169				compatible = "openisa,rv32m1-intmux-ch";
170				#address-cells = <0>;
171				#interrupt-cells = <1>;
172				interrupt-controller;
173				interrupts = <INTMUX_CH7_IRQ>;
174				reg = <0x1c0 0x40>;
175				status = "disabled";
176			};
177		};
178
179		intmux1: intmux@41022000 {
180			compatible = "openisa,rv32m1-intmux";
181			reg = <0x41022000 0x20>;
182			clocks = <&pcc1 0x88>;
183			status = "disabled";
184			#address-cells = <1>;
185			#size-cells = <1>;
186
187			ranges = <0x0 0x41022000 0x200>;
188
189			intmux1_ch0: interrupt-controller@0 {
190				compatible = "openisa,rv32m1-intmux-ch";
191				#address-cells = <0>;
192				#interrupt-cells = <1>;
193				interrupt-controller;
194				interrupts = <INTMUX_CH0_IRQ>;
195				reg = <0x0 0x40>;
196				status = "disabled";
197			};
198
199			intmux1_ch1: interrupt-controller@40 {
200				compatible = "openisa,rv32m1-intmux-ch";
201				#address-cells = <0>;
202				#interrupt-cells = <1>;
203				interrupt-controller;
204				interrupts = <INTMUX_CH1_IRQ>;
205				reg = <0x40 0x40>;
206				status = "disabled";
207			};
208
209			intmux1_ch2: interrupt-controller@80 {
210				compatible = "openisa,rv32m1-intmux-ch";
211				#address-cells = <0>;
212				#interrupt-cells = <1>;
213				interrupt-controller;
214				interrupts = <INTMUX_CH2_IRQ>;
215				reg = <0x80 0x40>;
216				status = "disabled";
217			};
218
219			intmux1_ch3: interrupt-controller@c0 {
220				compatible = "openisa,rv32m1-intmux-ch";
221				#address-cells = <0>;
222				#interrupt-cells = <1>;
223				interrupt-controller;
224				interrupts = <INTMUX_CH3_IRQ>;
225				reg = <0xc0 0x40>;
226				status = "disabled";
227			};
228
229			intmux1_ch4: interrupt-controller@100 {
230				compatible = "openisa,rv32m1-intmux-ch";
231				#address-cells = <0>;
232				#interrupt-cells = <1>;
233				interrupt-controller;
234				interrupts = <INTMUX_CH4_IRQ>;
235				reg = <0x100 0x40>;
236				status = "disabled";
237			};
238
239			intmux1_ch5: interrupt-controller@140 {
240				compatible = "openisa,rv32m1-intmux-ch";
241				#address-cells = <0>;
242				#interrupt-cells = <1>;
243				interrupt-controller;
244				interrupts = <INTMUX_CH5_IRQ>;
245				reg = <0x140 0x40>;
246				status = "disabled";
247			};
248
249			intmux1_ch6: interrupt-controller@180 {
250				compatible = "openisa,rv32m1-intmux-ch";
251				#address-cells = <0>;
252				#interrupt-cells = <1>;
253				interrupt-controller;
254				interrupts = <INTMUX_CH6_IRQ>;
255				reg = <0x180 0x40>;
256				status = "disabled";
257			};
258
259			intmux1_ch7: interrupt-controller@1c0 {
260				compatible = "openisa,rv32m1-intmux-ch";
261				#address-cells = <0>;
262				#interrupt-cells = <1>;
263				interrupt-controller;
264				interrupts = <INTMUX_CH7_IRQ>;
265				reg = <0x1c0 0x40>;
266				status = "disabled";
267			};
268		};
269
270		lptmr0: timer@40032000 {
271			compatible = "openisa,rv32m1-lptmr";
272			reg = <0x40032000 0x10>;
273		};
274
275		lptmr1: timer@40033000 {
276			compatible = "openisa,rv32m1-lptmr";
277			reg = <0x40033000 0x10>;
278		};
279
280		lptmr2: timer@4102b000 {
281			compatible = "openisa,rv32m1-lptmr";
282			reg = <0x4102b000 0x10>;
283		};
284
285		porta: pinmux@40046000 {
286			compatible = "openisa,rv32m1-pinmux";
287			reg = <0x40046000 0xd0>;
288			clocks = <&pcc0 0x118>;
289		};
290
291		portb: pinmux@40047000 {
292			compatible = "openisa,rv32m1-pinmux";
293			reg = <0x40047000 0xd0>;
294			clocks = <&pcc0 0x11c>;
295		};
296
297		portc: pinmux@40048000 {
298			compatible = "openisa,rv32m1-pinmux";
299			reg = <0x40048000 0xd0>;
300			clocks = <&pcc0 0x120>;
301		};
302
303		portd: pinmux@40049000 {
304			compatible = "openisa,rv32m1-pinmux";
305			reg = <0x40049000 0xd0>;
306			clocks = <&pcc0 0x124>;
307		};
308
309		porte: pinmux@41037000 {
310			compatible = "openisa,rv32m1-pinmux";
311			reg = <0x41037000 0xd0>;
312			clocks = <&pcc1 0xdc>;
313		};
314
315		gpioa: gpio@48020000 {
316			compatible = "openisa,rv32m1-gpio";
317			reg = <0x48020000 0x14>;
318			gpio-controller;
319			#gpio-cells = <2>;
320			openisa,rv32m1-port = <&porta>;
321		};
322
323		gpiob: gpio@48020040 {
324			compatible = "openisa,rv32m1-gpio";
325			reg = <0x48020040 0x14>;
326			gpio-controller;
327			#gpio-cells = <2>;
328			openisa,rv32m1-port = <&portb>;
329		};
330
331		gpioc: gpio@48020080 {
332			compatible = "openisa,rv32m1-gpio";
333			reg = <0x48020080 0x14>;
334			gpio-controller;
335			#gpio-cells = <2>;
336			openisa,rv32m1-port = <&portc>;
337		};
338
339		gpiod: gpio@480200c0 {
340			compatible = "openisa,rv32m1-gpio";
341			reg = <0x480200c0 0x14>;
342			gpio-controller;
343			#gpio-cells = <2>;
344			openisa,rv32m1-port = <&portd>;
345		};
346
347		gpioe: gpio@4100f000 {
348			compatible = "openisa,rv32m1-gpio";
349			reg = <0x4100f000 0x14>;
350			gpio-controller;
351			#gpio-cells = <2>;
352			clocks = <&pcc1 0x3c>;
353			openisa,rv32m1-port = <&porte>;
354		};
355
356		lpuart0: lpuart@40042000 {
357			compatible = "openisa,rv32m1-lpuart";
358			reg = <0x40042000 0x2c>;
359			clocks = <&pcc0 0x108>;
360			status = "disabled";
361		};
362
363		lpuart1: lpuart@40043000 {
364			compatible = "openisa,rv32m1-lpuart";
365			reg = <0x40043000 0x2c>;
366			clocks = <&pcc0 0x10c>;
367			status = "disabled";
368		};
369
370		lpuart2: lpuart@40044000 {
371			compatible = "openisa,rv32m1-lpuart";
372			reg = <0x40044000 0x2c>;
373			clocks = <&pcc0 0x110>;
374			status = "disabled";
375		};
376
377		lpuart3: lpuart@41036000 {
378			compatible = "openisa,rv32m1-lpuart";
379			reg = <0x41036000 0x2c>;
380			clocks = <&pcc0 0xd8>;
381			status = "disabled";
382		};
383
384		lpi2c0: lpi2c@4003a000 {
385			compatible = "openisa,rv32m1-lpi2c";
386			reg = <0x4003a000 0x170>;
387			clocks = <&pcc0 0xe8>;
388			clock-frequency = <I2C_BITRATE_STANDARD>;
389			#address-cells = <1>;
390			#size-cells = <0>;
391			status = "disabled";
392		};
393
394		lpi2c1: lpi2c@4003b000 {
395			compatible = "openisa,rv32m1-lpi2c";
396			reg = <0x4003b000 0x170>;
397			clocks = <&pcc0 0xec>;
398			clock-frequency = <I2C_BITRATE_STANDARD>;
399			#address-cells = <1>;
400			#size-cells = <0>;
401			status = "disabled";
402		};
403
404		lpi2c2: lpi2c@4003c000 {
405			compatible = "openisa,rv32m1-lpi2c";
406			reg = <0x4003c000 0x170>;
407			clocks = <&pcc0 0xf0>;
408			clock-frequency = <I2C_BITRATE_STANDARD>;
409			#address-cells = <1>;
410			#size-cells = <0>;
411			status = "disabled";
412		};
413
414		lpi2c3: lpi2c@4102e000 {
415			compatible = "openisa,rv32m1-lpi2c";
416			reg = <0x4102e000 0x170>;
417			clocks = <&pcc1 0xb8>;
418			clock-frequency = <I2C_BITRATE_STANDARD>;
419			#address-cells = <1>;
420			#size-cells = <0>;
421			status = "disabled";
422		};
423
424		lpspi0: spi@4003f000 {
425			compatible = "openisa,rv32m1-lpspi";
426			reg = <0x4003f000 0x78>;
427			status = "disabled";
428			clocks = <&pcc0 0xfc>;
429			#address-cells = <1>;
430			#size-cells = <0>;
431		};
432
433		lpspi1: spi@40040000 {
434			compatible = "openisa,rv32m1-lpspi";
435			reg = <0x40040000 0x78>;
436			status = "disabled";
437			clocks = <&pcc0 0x100>;
438			#address-cells = <1>;
439			#size-cells = <0>;
440		};
441
442		lpspi2: spi@40041000 {
443			compatible = "openisa,rv32m1-lpspi";
444			reg = <0x40041000 0x78>;
445			status = "disabled";
446			clocks = <&pcc0 0x104>;
447			#address-cells = <1>;
448			#size-cells = <0>;
449		};
450
451		lpspi3: spi@41035000 {
452			compatible = "openisa,rv32m1-lpspi";
453			reg = <0x41035000 0x78>;
454			status = "disabled";
455			clocks = <&pcc1 0xd4>;
456			#address-cells = <1>;
457			#size-cells = <0>;
458		};
459
460		generic_fsk: generic_fsk@41033000 {
461			compatible = "openisa,rv32m1-genfsk";
462			reg = <0x41033000 0x90>;
463			#address-cells = <1>;
464			#size-cells = <0>;
465		};
466
467		tpm0: pwm@40035000 {
468			compatible = "openisa,rv32m1-tpm";
469			reg = <0x40035000 0x88>;
470			clocks = <&pcc0 0xd4>;
471			status = "disabled";
472			#pwm-cells = <3>;
473		};
474
475		tpm1: pwm@40036000 {
476			compatible = "openisa,rv32m1-tpm";
477			reg = <0x40036000 0x88>;
478			clocks = <&pcc0 0xd8>;
479			status = "disabled";
480			#pwm-cells = <3>;
481		};
482
483		tpm2: pwm@40037000 {
484			compatible = "openisa,rv32m1-tpm";
485			reg = <0x40037000 0x88>;
486			clocks = <&pcc0 0xdc>;
487			status = "disabled";
488			#pwm-cells = <3>;
489		};
490
491		trng: random@41029000{
492			compatible = "openisa,rv32m1-trng";
493			reg = <0x41029000 0x1000>;
494			status = "okay";
495			interrupts = <13 0>;
496		};
497
498		tpm3: pwm@4102d000 {
499			compatible = "openisa,rv32m1-tpm";
500			reg = <0x4102d000 0x88>;
501			clocks = <&pcc1 0xb4>;
502			status = "disabled";
503			#pwm-cells = <3>;
504		};
505
506		ftfe: flash-controller@40023000 {
507			compatible = "openisa,rv32m1-ftfe";
508			reg = <0x40023000 0x18>;
509
510			#address-cells = <1>;
511			#size-cells = <1>;
512
513			m4_flash: flash@0 {
514				compatible = "soc-nv-flash";
515				reg = <0 0x100000>;
516				erase-block-size = <4096>;
517				write-block-size = <8>;
518			};
519
520			m0_flash: flash@1000000 {
521				compatible = "soc-nv-flash";
522				reg = <0x01000000 0x40000>;
523				erase-block-size = <4096>;
524				write-block-size = <8>;
525			};
526		};
527	};
528};
529