1# Copyright (c) 2023 SLB
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  Infineon XMC4XXX PWM Capture Compare Unit 4 (CCU4) module
6
7  The are four CCU4 modules with dts node labels:
8  pwm_ccu40, pwm_ccu41, pwm_ccu42, pwm_ccu43.
9  Each module has four slices and each slice has one channel.
10  A channel is connected to a particular gpio pin, which are defined
11  using pinctrl in:
12  dts/arm/infineon/xmc4xxx_xxx-pinctrl.dtsi
13
14  The CCU4 modules uses the CCU clock source. Each slice applies a separate
15  prescalar which divides the clock.
16
17  Device tree example:
18  A node can define a 'pwm' field, usually referenced in a 'pwms'
19  property, where the entries include the PWM module phandle,
20  channel number, pulse period (in nanoseconds or set using
21  PWM_XX() macros), and a channela
22  flag (PWM_POLARITY_NORMAL/PWM_POLARITY_INVERTED).
23
24  The pwm ccu4 node must define the slice-prescaler values and the pinctrl nodes:
25  &pwm_ccu40 {
26      slice-prescaler = <15 15 15 15>;
27      pinctrl-0 = <&pwm_out_p1_1_ccu40_ch2>;
28      pinctrl-names = "default";
29  };
30
31  Another node can reference the PWM as follows:
32  &test_node {
33     ...
34     pwms = <&pwm_ccu40 0 PWM_SEC(1) PWM_POLARITY_NORMAL>;
35     ...
36  };
37
38  The user must also explicitly set pinctrl properties.
39  The pin should be configured with drive-push-pull bool option and hwctrl should be set
40  to disabled. The drive-strength field can be set to any of the supported values:
41  &pwm_out_p1_1_ccu40_ch2 {
42      drive-strength = "strong-medium-edge";
43      drive-push-pull;
44      hwctrl = "disabled";
45  };
46
47  The CCU4 pinctrl nodes have a node labels in the format
48  pwm_out_p{PORT}_{PIN}_ccu4{MODULE_IDX}_ch{CHANNEL_IDX}, where MODULE_IDX and
49  CHANNEL_IDX refers to specific pwm_ccu4x module and channel, respectively.
50  PORT/PIN pair defines what gpio the channel connects to.
51
52compatible: "infineon,xmc4xxx-ccu4-pwm"
53
54include:
55  - name: base.yaml
56  - name: pwm-controller.yaml
57  - name: pinctrl-device.yaml
58
59properties:
60  reg:
61    required: true
62
63  pinctrl-0:
64    required: true
65
66  pinctrl-names:
67    required: true
68
69  slice-prescaler:
70    type: array
71    required: true
72    description: |
73      Defines the clock divider for each channel.
74      The entry in the array will divide CCU clock by (2 << value).
75      The range for the prescaler values is [0, 15].
76      Reducing prescaler value will improve resolution but decrease the maximum period.
77
78  "#pwm-cells":
79    const: 3
80
81pwm-cells:
82  - channel
83  - period
84  - flags
85