1# Copyright (c) 2023 Nordic Semiconductor ASA
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5    The TI CC32XX pin controller is a singleton node responsible for controlling
6    pin function selection and pin properties. For example, you can
7    use this node to route UART0 RX to pin 55 and enable the pull-up resistor
8    on the pin.
9
10    The node has the 'pinctrl' node label set in your SoC's devicetree,
11    so you can modify it like this:
12
13      &pinctrl {
14              /* your modifications go here */
15      };
16
17    All device pin configurations should be placed in child nodes of the
18    'pinctrl' node, as shown in this example:
19
20      /* You can put this in places like a board-pinctrl.dtsi file in
21       * your board directory, or a devicetree overlay in your application.
22       */
23
24      /* include pre-defined combinations for the SoC variant used by the board */
25      #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
26
27      &pinctrl {
28        /* configuration for the uart0 "default" state */
29        uart0_default: uart0_default {
30          /* group 1 */
31          group1 {
32            /* configure pin 55 as UART0 TX and pin 61 as UART0 CTS */
33            pinmux = <UART0_TX_P55>, <UART0_CTS_P61>;
34          };
35          /* group 2 */
36          group2 {
37            /* configure pin 57 as UART0 RX and pin 62 as UART0 RTS  */
38            pinmux = <UART0_RX_P57>, <UART0_RTS_P62>;
39            /* both pin 57 and 62 have pull-up enabled */
40            bias-pull-up;
41          };
42        };
43
44    The 'uart0_default' child node encodes the pin configurations for a
45    particular state of a device; in this case, the default (that is, active)
46    state.
47
48    As shown, pin configurations are organized in groups within each child node.
49    Each group can specify a list of pin function selections in the 'pinmux'
50    property.
51
52    A group can also specify shared pin properties common to all the specified
53    pins, such as the 'bias-pull-up' property in group 2. Here is a list of
54    supported standard pin properties:
55
56    - drive-push-pull: Push-pull drive mode (default, not required).
57    - drive-open-drain: Open-drain drive mode.
58    - bias-disable: Disable pull-up/down (default, not required).
59    - bias-pull-up: Enable pull-up resistor.
60    - bias-pull-down: Enable pull-down resistor.
61    - drive-strength: Configure drive strength in mA (defaults to 6mA, IC default).
62
63    Note that drive and bias options are mutually exclusive.
64
65    To link pin configurations with a device, use a pinctrl-N property for some
66    number N, like this example you could place in your board's DTS file:
67
68       #include "board-pinctrl.dtsi"
69
70       &uart0 {
71             pinctrl-0 = <&uart0_default>
72             pinctrl-names = "default";
73       };
74
75compatible: "ti,cc32xx-pinctrl"
76
77include: base.yaml
78
79child-binding:
80  child-binding:
81    include:
82      - name: pincfg-node.yaml
83        property-allowlist:
84          - drive-push-pull
85          - drive-open-drain
86          - bias-disable
87          - bias-pull-down
88          - bias-pull-up
89          - drive-strength
90
91    properties:
92      pinmux:
93        required: true
94        type: array
95        description: |
96          An array of pins sharing the same group properties. The pins should
97          be defined using pre-defined macros or, alternatively, using the
98          TI_CC32XX_PINMUX helper macro.
99
100      drive-strength:
101        default: 6
102        enum:
103          - 0
104          - 2
105          - 4
106          - 6
107          - 8
108          - 10
109          - 12
110          - 14
111