1description: Xilinx AXI GPIO IP node
2
3compatible: "xlnx,xps-gpio-1.00.a"
4
5include: [gpio-controller.yaml, base.yaml]
6
7bus: xlnx,xps-gpio-1.00.a
8
9# Property names correspond to a subset of those generated by
10# https://github.com/Xilinx/device-tree-xlnx
11
12properties:
13  reg:
14    required: true
15
16  xlnx,all-inputs:
17    type: int
18    description: |
19      1 if all GPIOs are inputs, 0 otherwise
20
21  xlnx,all-outputs:
22    type: int
23    description: |
24      1 if all GPIOs are outputs, 0 otherwise
25
26  xlnx,dout-default:
27    type: int
28    description: |
29      Default output value. If n-th bit is 1, GPIO-n default value is 1.
30
31  xlnx,gpio-width:
32    type: int
33    description: |
34      Number of GPIOs supported
35
36  xlnx,tri-default:
37    type: int
38    description: |
39      Default tristate register value. If n-th bit is 1, GPIO-n is an input.
40
41  xlnx,is-dual:
42    type: int
43    description: |
44      1 if controller has GPIO2 enabled, 0 otherwise
45
46  xlnx,all-inputs-2:
47    type: int
48    description: |
49      1 if all GPIO2s are inputs, 0 otherwise
50
51  xlnx,all-outputs-2:
52    type: int
53    description: |
54      1 if all GPIO2s are outputs, 0 otherwise
55
56  xlnx,dout-default-2:
57    type: int
58    description: |
59      Default output value. If n-th bit is 1, GPIO2-n default value is 1.
60
61  xlnx,gpio2-width:
62    type: int
63    description: |
64      Number of GPIO2s supported
65
66  xlnx,tri-default-2:
67    type: int
68    description: |
69      Default tristate register value. If n-th bit is 1, GPIO2-n is an input.
70
71  "#gpio-cells":
72    const: 2
73
74gpio-cells:
75  - pin
76  - flags
77