1/*
2 * Copyright (c) 2023 Enphase Energy
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <freq.h>
9#include <arm64/armv8-a.dtsi>
10#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
11#include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
12
13/ {
14	#address-cells = <1>;
15	#size-cells = <1>;
16
17	cpus {
18		#address-cells = <1>;
19		#size-cells = <0>;
20
21		cpu@0 {
22			device_type = "cpu";
23			compatible = "arm,cortex-a53";
24			reg = <0>;
25		};
26	};
27
28	oc_sram: memory@70000000 {
29		reg = <0x70000000 DT_SIZE_K(64)>;
30	};
31
32	arch_timer: timer {
33		compatible = "arm,armv8-timer";
34		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
35				  IRQ_DEFAULT_PRIORITY>,
36				 <GIC_PPI 14 IRQ_TYPE_LEVEL
37				  IRQ_DEFAULT_PRIORITY>,
38				 <GIC_PPI 11 IRQ_TYPE_LEVEL
39				  IRQ_DEFAULT_PRIORITY>,
40				 <GIC_PPI 10 IRQ_TYPE_LEVEL
41				  IRQ_DEFAULT_PRIORITY>;
42		interrupt-parent = <&gic>;
43	};
44
45	gic: interrupt-controller@1800000 {
46		compatible = "arm,gic-v3", "arm,gic";
47		reg = <0x01800000 0x10000>, /* GICD */
48			  <0x01880000 0xc0000>; /* GICR */
49		interrupt-controller;
50		#interrupt-cells = <4>;
51		status = "okay";
52	};
53
54	pinctrl: pinctrl@f4000 {
55		compatible = "ti,k3-pinctrl";
56		reg = <0x000f4000 0x2ac>;
57		status = "okay";
58	};
59
60	uart0: serial@2800000 {
61		compatible = "ns16550";
62		reg = <0x02800000 0x100>;
63		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
64		interrupt-parent = <&gic>;
65		clock-frequency = <48000000>;
66		current-speed = <115200>;
67		reg-shift = <2>;
68		status = "disabled";
69	};
70
71	uart1: serial@2810000 {
72		compatible = "ns16550";
73		reg = <0x02810000 0x100>;
74		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
75		interrupt-parent = <&gic>;
76		clock-frequency = <48000000>;
77		current-speed = <115200>;
78		reg-shift = <2>;
79		status = "disabled";
80	};
81
82	uart2: serial@2820000 {
83		compatible = "ns16550";
84		reg = <0x02820000 0x100>;
85		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
86		interrupt-parent = <&gic>;
87		clock-frequency = <48000000>;
88		current-speed = <115200>;
89		reg-shift = <2>;
90		status = "disabled";
91	};
92
93	uart3: serial@2830000 {
94		compatible = "ns16550";
95		reg = <0x02830000 0x100>;
96		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
97		interrupt-parent = <&gic>;
98		clock-frequency = <48000000>;
99		current-speed = <115200>;
100		reg-shift = <2>;
101		status = "disabled";
102	};
103
104	uart4: serial@2840000 {
105		compatible = "ns16550";
106		reg = <0x02840000 0x100>;
107		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
108		interrupt-parent = <&gic>;
109		clock-frequency = <48000000>;
110		current-speed = <115200>;
111		reg-shift = <2>;
112		status = "disabled";
113	};
114
115	uart5: serial@2850000 {
116		compatible = "ns16550";
117		reg = <0x02850000 0x100>;
118		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
119		interrupt-parent = <&gic>;
120		clock-frequency = <48000000>;
121		current-speed = <115200>;
122		reg-shift = <2>;
123		status = "disabled";
124	};
125
126	uart6: serial@2860000 {
127		compatible = "ns16550";
128		reg = <0x02860000 0x100>;
129		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
130		interrupt-parent = <&gic>;
131		clock-frequency = <48000000>;
132		current-speed = <115200>;
133		reg-shift = <2>;
134		status = "disabled";
135	};
136};
137