1/*
2 * Copyright 2022 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <freq.h>
9#include <arm64/armv8-a.dtsi>
10#include <zephyr/dt-bindings/clock/imx_ccm.h>
11#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
12
13/ {
14	#address-cells = <1>;
15	#size-cells = <1>;
16
17	chosen {
18		zephyr,console = &uart2;
19		zephyr,shell-uart = &uart2;
20	};
21
22	cpus {
23		#address-cells = <1>;
24		#size-cells = <0>;
25
26		cpu@0 {
27			device_type = "cpu";
28			compatible = "arm,cortex-a53";
29			reg = <0>;
30		};
31
32		cpu@1 {
33			device_type = "cpu";
34			compatible = "arm,cortex-a53";
35			reg = <1>;
36		};
37
38		cpu@2 {
39			device_type = "cpu";
40			compatible = "arm,cortex-a53";
41			reg = <2>;
42		};
43
44		cpu@3 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a53";
47			reg = <3>;
48		};
49
50	};
51
52	arch_timer: timer {
53		compatible = "arm,armv8-timer";
54		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
55			      IRQ_DEFAULT_PRIORITY>,
56			     <GIC_PPI 14 IRQ_TYPE_LEVEL
57			      IRQ_DEFAULT_PRIORITY>,
58			     <GIC_PPI 11 IRQ_TYPE_LEVEL
59			      IRQ_DEFAULT_PRIORITY>,
60			     <GIC_PPI 10 IRQ_TYPE_LEVEL
61			      IRQ_DEFAULT_PRIORITY>;
62		interrupt-parent = <&gic>;
63	};
64
65	gic: interrupt-controller@38800000 {
66		compatible = "arm,gic-v3", "arm,gic";
67		reg = <0x38800000 0x10000>, /* GIC Dist */
68		      <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
69		interrupt-controller;
70		#interrupt-cells = <4>;
71		status = "okay";
72	};
73
74	iomuxc: iomuxc@30330000 {
75		compatible = "nxp,imx-iomuxc";
76		reg = <0x30330000 DT_SIZE_K(64)>;
77		status = "okay";
78		pinctrl: pinctrl {
79			status = "okay";
80			compatible = "nxp,imx8m-pinctrl";
81		};
82	};
83
84	ana_pll: ana_pll@30360000 {
85		compatible = "nxp,imx-ana";
86		reg = <0x30360000 DT_SIZE_K(64)>;
87	};
88
89	ccm: ccm@30380000 {
90		compatible = "nxp,imx-ccm";
91		reg = <0x30380000 DT_SIZE_K(64)>;
92		#clock-cells = <3>;
93	};
94
95	uart2: serial@30890000 {
96		compatible = "nxp,imx-iuart";
97		reg = <0x30890000 DT_SIZE_K(64)>;
98		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
99		interrupt-names = "irq_0";
100		interrupt-parent = <&gic>;
101		clocks = <&ccm IMX_CCM_UART2_CLK 0x6c 24>;
102		status = "disabled";
103	};
104
105	uart4: serial@30a60000 {
106		compatible = "nxp,imx-iuart";
107		reg = <0x30a60000 DT_SIZE_K(64)>;
108		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
109		interrupt-names = "irq_0";
110		interrupt-parent = <&gic>;
111		clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>;
112		status = "disabled";
113	};
114};
115