1/*
2 * Copyright (c) 2020 Paul M. Bendixen
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <st/f3/stm32f303.dtsi>
9
10/ {
11	ccm0: memory@10000000 {
12		compatible = "zephyr,memory-region", "st,stm32-ccm";
13		reg = <0x10000000 DT_SIZE_K(16)>;
14		zephyr,memory-region = "CCM";
15	};
16
17	sram0: memory@20000000 {
18		reg = <0x20000000 DT_SIZE_K(64)>;
19	};
20
21	soc {
22		flash-controller@40022000 {
23			flash0: flash@8000000 {
24				reg = <0x08000000 DT_SIZE_K(512)>;
25			};
26		};
27
28		dma2: dma@40020400 {
29			compatible = "st,stm32-dma-v2bis";
30			#dma-cells = <2>;
31			reg = <0x40020400 0x400>;
32			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
33			interrupts = <56 0 57 0 58 0 59 0 60 0>;
34			status = "disabled";
35		};
36
37		rtc@40002800 {
38			bbram: backup_regs {
39				compatible = "st,stm32-bbram";
40				st,backup-regs = <16>;
41				status = "disabled";
42			};
43		};
44	};
45};
46