1/*
2 * Copyright (c) 2020 TriaGnoSys GmbH
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv8-m.dtsi>
8#include <dt-bindings/gpio/gpio.h>
9#include <arm/silabs/gpio_gecko.h>
10#include <dt-bindings/i2c/i2c.h>
11#include <dt-bindings/pinctrl/gecko-pinctrl.h>
12#include <dt-bindings/adc/adc.h>
13#include <freq.h>
14
15/ {
16	chosen {
17		zephyr,flash-controller = &msc;
18		zephyr,entropy = &se;
19	};
20
21	clocks {
22		clk_hfxo: clk-hfxo {
23			#clock-cells = <0>;
24			compatible = "silabs,hfxo";
25			clock-frequency = <DT_FREQ_M(39)>;
26			ctune = <140>;
27			precision = <50>;
28		};
29	};
30
31	cpus {
32		#address-cells = <1>;
33		#size-cells = <0>;
34
35		cpu0: cpu@0 {
36			device_type = "cpu";
37			compatible = "arm,cortex-m33";
38			reg = <0>;
39			cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>;
40		};
41
42		power-states {
43			/*
44			 * EM1 is a basic "CPU WFI idle", all high-freq clocks remain
45			 * enabled.
46			 */
47			pstate_em1: em1 {
48				compatible = "zephyr,power-state";
49				power-state-name = "runtime-idle";
50				min-residency-us = <4>;
51				/* HFXO remains active */
52				exit-latency-us = <2>;
53			};
54
55			/*
56			 * EM2 is a deepsleep with HF clocks disabled by HW, voltages
57			 * scaled down, etc.
58			 */
59			pstate_em2: em2 {
60				compatible = "zephyr,power-state";
61				power-state-name = "suspend-to-idle";
62				min-residency-us = <260>;
63				exit-latency-us = <250>;
64			};
65
66			/*
67			 * EM3 seems to be exactly the same as EM2 except that
68			 * LFXO & LFRCO should be disabled, so you must use ULFRCO
69			 * as BURTC clock for the system to not lose track of time and
70			 * wake up.
71			 */
72			pstate_em3: em3 {
73				compatible = "zephyr,power-state";
74				power-state-name = "standby";
75				min-residency-us = <20000>;
76				exit-latency-us = <2000>;
77			};
78		};
79	};
80
81	sram0: memory@20000000 {
82		device_type = "memory";
83		compatible = "mmio-sram";
84	};
85
86	soc {
87		msc: flash-controller@50030000 {
88			compatible = "silabs,gecko-flash-controller";
89			reg = <0x50030000 0x3148>;
90			interrupts = <50 0>;
91
92			#address-cells = <1>;
93			#size-cells = <1>;
94
95			flash0: flash@0 {
96				compatible = "soc-nv-flash";
97				write-block-size = <4>;
98				erase-block-size = <8192>;
99			};
100		};
101
102		usart0: usart@5005c000 {
103			compatible = "silabs,gecko-usart";
104			reg = <0x5005C000 0x306c>;
105			interrupts = <9 0>, <10 0>;
106			interrupt-names = "rx", "tx";
107			peripheral-id = <0>;
108			status = "disabled";
109		};
110
111		burtc0: burtc@50064000 {
112			compatible = "silabs,gecko-burtc";
113			reg = <0x50064000 0x3034>;
114			interrupts = <17 0>;
115			status = "disabled";
116		};
117
118		se: semailbox@5c021000 {
119			compatible = "silabs,gecko-semailbox";
120			reg = <0x5c021000 0x1000>;
121			status = "disabled";
122			interrupts = <64 3>, <65 3>, <66 3>;
123			interrupt-names = "SETAMPERHOST", "SEMBRX", "SEMBTX";
124		};
125
126		i2c0: i2c@5b000000 {
127			compatible = "silabs,gecko-i2c";
128			clock-frequency = <I2C_BITRATE_STANDARD>;
129			#address-cells = <1>;
130			#size-cells = <0>;
131			reg = <0x5b000000 0x3044>;
132			interrupts = <27 0>;
133			status = "disabled";
134		};
135
136		stimer0: stimer@500a8000 {
137			compatible = "silabs,gecko-stimer";
138			reg = <0x500a8000 0x3054>;
139			interrupts = <67 0>;
140			clock-frequency = <32768>;
141			prescaler = <1>;
142			status = "disabled";
143		};
144
145		gpio: gpio@5003c000 {
146			compatible = "silabs,gecko-gpio";
147			reg = <0x5003c000 0x4000>;
148			interrupts = <26 2>, <25 2>;
149			interrupt-names = "GPIO_EVEN", "GPIO_ODD";
150
151			ranges;
152			#address-cells = <1>;
153			#size-cells = <1>;
154
155			gpioa: gpio@5003c030 {
156				compatible = "silabs,gecko-gpio-port";
157				reg = <0x5003c030 0x30>;
158				peripheral-id = <0>;
159				gpio-controller;
160				#gpio-cells = <2>;
161				status = "disabled";
162			};
163
164			gpiob: gpio@5003c060 {
165				compatible = "silabs,gecko-gpio-port";
166				reg = <0x5003c060 0x30>;
167				peripheral-id = <1>;
168				gpio-controller;
169				#gpio-cells = <2>;
170				status = "disabled";
171			};
172
173			gpioc: gpio@5003c090 {
174				compatible = "silabs,gecko-gpio-port";
175				reg = <0x5003c090 0x30>;
176				peripheral-id = <2>;
177				gpio-controller;
178				#gpio-cells = <2>;
179				status = "disabled";
180			};
181
182			gpiod: gpio@5003c0C0 {
183				compatible = "silabs,gecko-gpio-port";
184				reg = <0x5003c0C0 0x30>;
185				peripheral-id = <3>;
186				gpio-controller;
187				#gpio-cells = <2>;
188				status = "disabled";
189			};
190		};
191
192		wdog0: wdog@5b004000 {
193			compatible = "silabs,gecko-wdog";
194			reg = <0x5b004000 0x2C>;
195			peripheral-id = <0>;
196			interrupts = <42 0>;
197			status = "disabled";
198		};
199
200		wdog1: wdog@5b008000 {
201			compatible = "silabs,gecko-wdog";
202			reg = <0x5b008000 0x2C>;
203			peripheral-id = <1>;
204			interrupts = <43 0>;
205			status = "disabled";
206		};
207
208		adc0: adc@59004000 {
209			compatible = "silabs,gecko-iadc";
210			reg = <0x59004000 0x4000>;
211			interrupts = <49 0>;
212			status = "disabled";
213			#io-channel-cells = <1>;
214		};
215	};
216};
217
218/ {
219	pinctrl: pin-controller {
220		/* Pin controller is a "virtual" device since SiLabs SoCs do pin
221		 * control in a distributed way (GPIO registers and PSEL
222		 * registers on each peripheral).
223		 */
224		compatible = "silabs,gecko-pinctrl";
225	};
226
227	hwinfo: hwinfo {
228		compatible = "silabs,gecko-hwinfo";
229		status = "disabled";
230	};
231
232};
233
234&nvic {
235	arm,num-irq-priority-bits = <4>;
236};
237