1/*
2 * Copyright 2017,2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv7-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/clock/imx_ccm.h>
11#include <zephyr/dt-bindings/gpio/gpio.h>
12#include <zephyr/dt-bindings/i2c/i2c.h>
13#include <zephyr/dt-bindings/pwm/pwm.h>
14#include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
15
16/ {
17	chosen {
18		zephyr,entropy = &trng;
19		die-temp0 = &tempmon;
20	};
21
22	cpus {
23		#address-cells = <1>;
24		#size-cells = <0>;
25
26		cpu0: cpu@0 {
27			device_type = "cpu";
28			compatible = "arm,cortex-m7";
29			d-cache-line-size = <32>;
30			reg = <0>;
31			cpu-power-states = <&idle &suspend>;
32			#address-cells = <1>;
33			#size-cells = <1>;
34
35			mpu: mpu@e000ed90 {
36				compatible = "arm,armv7m-mpu";
37				reg = <0xe000ed90 0x40>;
38			};
39
40			itm: itm@e0000000 {
41				compatible = "arm,armv7m-itm";
42				reg = <0xe0000000 0x1000>;
43				swo-ref-frequency = <132000000>;
44			};
45		};
46
47		power-states {
48			idle: idle {
49				compatible = "zephyr,power-state";
50				power-state-name = "runtime-idle";
51				exit-latency-us = <4000>;
52				min-residency-us = <5000>;
53			};
54			suspend: suspend {
55				compatible = "zephyr,power-state";
56				power-state-name = "suspend-to-idle";
57				exit-latency-us = <5000>;
58				min-residency-us = <10000>;
59			};
60		};
61	};
62
63	sysclk: system-clock {
64		compatible = "fixed-clock";
65		clock-frequency = <600000000>;
66		#clock-cells = <0>;
67	};
68
69	xtal: clock-xtal {
70		compatible = "fixed-clock";
71		clock-frequency = <24000000>;
72		#clock-cells = <0>;
73	};
74
75	rtc_xtal: clock-rtc-xtal {
76		compatible = "fixed-clock";
77		clock-frequency = <32768>;
78		#clock-cells = <0>;
79	};
80
81	/* USB PLL (selected to be FLEXSPI clock source) will be left unchanged */
82	usbclk: usbpll-clock {
83		compatible = "fixed-clock";
84		clock-frequency = <480000000>;
85		#clock-cells = <0>;
86	};
87
88	soc {
89		flexram: flexram@400b0000 {
90			compatible = "nxp,flexram";
91			reg = <0x400b0000 0x4000>;
92			interrupts = <38 0>;
93
94			#address-cells = <1>;
95			#size-cells = <1>;
96
97			status = "okay";
98
99			flexram,bank-size = <32>;
100
101			itcm: itcm@0 {
102				compatible = "zephyr,memory-region", "nxp,imx-itcm";
103				reg = <0x00000000 DT_SIZE_K(128)>;
104				zephyr,memory-region = "ITCM";
105			};
106
107			dtcm: dtcm@20000000 {
108				compatible = "zephyr,memory-region", "nxp,imx-dtcm";
109				reg = <0x20000000 DT_SIZE_K(128)>;
110				zephyr,memory-region = "DTCM";
111			};
112
113			ocram: ocram@20200000 {
114				compatible = "zephyr,memory-region", "mmio-sram";
115				reg = <0x20200000 DT_SIZE_K(256)>;
116				zephyr,memory-region = "OCRAM";
117			};
118		};
119
120		flexspi: spi@402a8000 {
121			compatible = "nxp,imx-flexspi";
122			reg = <0x402a8000 0x4000>;
123			interrupts = <108 0>;
124			#address-cells = <1>;
125			#size-cells = <0>;
126			ahb-bufferable;
127			ahb-cacheable;
128			status = "disabled";
129			clocks = <&ccm IMX_CCM_FLEXSPI_CLK 0x0 0x0>;
130		};
131
132		flexspi2: spi@402a4000 {
133			compatible = "nxp,imx-flexspi";
134			reg = <0x402a4000 0x4000>;
135			interrupts = <107 0>;
136			#address-cells = <1>;
137			#size-cells = <0>;
138			ahb-bufferable;
139			ahb-cacheable;
140			status = "disabled";
141			clocks = <&ccm IMX_CCM_FLEXSPI2_CLK 0x0 0x0>;
142		};
143
144		semc: semc0@402f0000 {
145			compatible = "nxp,imx-semc";
146			reg = <0x402f0000 0x4000>;
147			interrupts = <109 0>;
148			#address-cells = <1>;
149			#size-cells = <1>;
150		};
151
152		/* GPT1 is used for the hardware timer, not as a standard counter */
153		gpt_hw_timer: gpt@401ec000 {
154			compatible = "nxp,gpt-hw-timer";
155			reg = <0x401ec000 0x4000>;
156			interrupts = <100 0>;
157			status = "disabled";
158		};
159
160		gpt2: gpt@401f0000 {
161			compatible = "nxp,imx-gpt";
162			reg = <0x401f0000 0x4000>;
163			interrupts = <101 0>;
164			gptfreq = <25000000>;
165			clocks = <&ccm IMX_CCM_GPT_CLK 0x68 24>;
166		};
167
168		qtmr1: qtmr@401dc000 {
169			compatible = "nxp,imx-qtmr";
170			reg = <0x401dc000 0x7a>;
171			interrupts = <133 0>;
172			clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
173			qtmr1_timer0: timer0 {
174				compatible = "nxp,imx-tmr";
175				channel = <0>;
176				status = "disabled";
177			};
178			qtmr1_timer1: timer1 {
179				compatible = "nxp,imx-tmr";
180				channel = <1>;
181				status = "disabled";
182			};
183			qtmr1_timer2: timer2 {
184				compatible = "nxp,imx-tmr";
185				channel = <2>;
186				status = "disabled";
187			};
188			qtmr1_timer3: timer3 {
189				compatible = "nxp,imx-tmr";
190				channel = <3>;
191				status = "disabled";
192			};
193		};
194
195		qtmr2: qtmr@401e0000 {
196			compatible = "nxp,imx-qtmr";
197			reg = <0x401e0000 0x7a>;
198			interrupts = <134 0>;
199			clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
200			qtmr2_timer0: timer0 {
201				compatible = "nxp,imx-tmr";
202				channel = <0>;
203				status = "disabled";
204			};
205			qtmr2_timer1: timer1 {
206				compatible = "nxp,imx-tmr";
207				channel = <1>;
208				status = "disabled";
209			};
210			qtmr2_timer2: timer2 {
211				compatible = "nxp,imx-tmr";
212				channel = <2>;
213				status = "disabled";
214			};
215			qtmr2_timer3: timer3 {
216				compatible = "nxp,imx-tmr";
217				channel = <3>;
218				status = "disabled";
219			};
220		};
221
222		qtmr3: qtmr@401e4000 {
223			compatible = "nxp,imx-qtmr";
224			reg = <0x401e4000 0x7a>;
225			interrupts = <135 0>;
226			clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
227			qtmr3_timer0: timer0 {
228				compatible = "nxp,imx-tmr";
229				channel = <0>;
230				status = "disabled";
231			};
232			qtmr3_timer1: timer1 {
233				compatible = "nxp,imx-tmr";
234				channel = <1>;
235				status = "disabled";
236			};
237			qtmr3_timer2: timer2 {
238				compatible = "nxp,imx-tmr";
239				channel = <2>;
240				status = "disabled";
241			};
242			qtmr3_timer3: timer3 {
243				compatible = "nxp,imx-tmr";
244				channel = <3>;
245				status = "disabled";
246			};
247		};
248
249		qtmr4: qtmr@401e8000 {
250			compatible = "nxp,imx-qtmr";
251			reg = <0x401e8000 0x7a>;
252			interrupts = <136 0>;
253			clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
254			qtmr4_timer0: timer0 {
255				compatible = "nxp,imx-tmr";
256				channel = <0>;
257				status = "disabled";
258			};
259			qtmr4_timer1: timer1 {
260				compatible = "nxp,imx-tmr";
261				channel = <1>;
262				status = "disabled";
263			};
264			qtmr4_timer2: timer2 {
265				compatible = "nxp,imx-tmr";
266				channel = <2>;
267				status = "disabled";
268			};
269			qtmr4_timer3: timer3 {
270				compatible = "nxp,imx-tmr";
271				channel = <3>;
272				status = "disabled";
273			};
274		};
275
276		ccm: ccm@400fc000 {
277			compatible = "nxp,imx-ccm";
278			reg = <0x400fc000 0x4000>;
279			clocks = <&xtal>, <&rtc_xtal>;
280			clock-names = "xtal", "rtc-xtal";
281
282			arm-podf {
283				compatible = "fixed-factor-clock";
284				clock-div = <1>;
285				#clock-cells = <0>;
286			};
287
288			ahb-podf {
289				compatible = "fixed-factor-clock";
290				clock-div = <1>;
291				#clock-cells = <0>;
292			};
293
294			ipg-podf {
295				compatible = "fixed-factor-clock";
296				clock-div = <1>;
297				#clock-cells = <0>;
298			};
299
300			#clock-cells = <3>;
301		};
302
303		snvs: snvs@400d4000 {
304			compatible = "nxp,imx-snvs";
305			reg = <0x400d4000 0x4000>;
306
307			snvs_rtc: rtc {
308				compatible = "nxp,imx-snvs-rtc";
309				interrupts = <46 0>;
310			};
311		};
312
313		gpio1: gpio@401b8000 {
314			compatible = "nxp,imx-gpio";
315			reg = <0x401b8000 0x4000>;
316			interrupts = <80 0>, <81 0>;
317			gpio-controller;
318			#gpio-cells = <2>;
319		};
320
321		gpio2: gpio@401bc000 {
322			compatible = "nxp,imx-gpio";
323			reg = <0x401bc000 0x4000>;
324			interrupts = <82 0>, <83 0>;
325			gpio-controller;
326			#gpio-cells = <2>;
327		};
328
329		gpio3: gpio@401c0000 {
330			compatible = "nxp,imx-gpio";
331			reg = <0x401c0000 0x4000>;
332			interrupts = <84 0>, <85 0>;
333			gpio-controller;
334			#gpio-cells = <2>;
335		};
336
337		gpio4: gpio@401c4000 {
338			compatible = "nxp,imx-gpio";
339			reg = <0x401c4000 0x4000>;
340			interrupts = <86 0>, <87 0>;
341			gpio-controller;
342			#gpio-cells = <2>;
343		};
344
345		gpio5: gpio@400c0000 {
346			compatible = "nxp,imx-gpio";
347			reg = <0x400c0000 0x4000>;
348			interrupts = <88 0>, <89 0>;
349			gpio-controller;
350			#gpio-cells = <2>;
351		};
352		/*
353		 * Note: interrupts for GPIO6-9 are not currently supported
354		 * by the gpio driver.
355		 */
356		gpio6: gpio@42000000 {
357			compatible = "nxp,imx-gpio";
358			reg = <0x42000000 0x4000>;
359			gpio-controller;
360			#gpio-cells = <2>;
361		};
362
363		gpio7: gpio@42004000 {
364			compatible = "nxp,imx-gpio";
365			reg = <0x42004000 0x4000>;
366			gpio-controller;
367			#gpio-cells = <2>;
368		};
369
370		gpio8: gpio@42008000 {
371			compatible = "nxp,imx-gpio";
372			reg = <0x42008000 0x4000>;
373			gpio-controller;
374			#gpio-cells = <2>;
375		};
376
377		gpio9: gpio@4200c000 {
378			compatible = "nxp,imx-gpio";
379			reg = <0x4200c000 0x4000>;
380			gpio-controller;
381			#gpio-cells = <2>;
382		};
383
384		lpi2c1: i2c@403f0000 {
385			compatible = "nxp,imx-lpi2c";
386			clock-frequency = <I2C_BITRATE_STANDARD>;
387			#address-cells = <1>;
388			#size-cells = <0>;
389			reg = <0x403f0000 0x4000>;
390			interrupts = <28 0>;
391			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 6>;
392			status = "disabled";
393		};
394
395		lpi2c2: i2c@403f4000 {
396			compatible = "nxp,imx-lpi2c";
397			clock-frequency = <I2C_BITRATE_STANDARD>;
398			#address-cells = <1>;
399			#size-cells = <0>;
400			reg = <0x403f4000 0x4000>;
401			interrupts = <29 0>;
402			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 8>;
403			status = "disabled";
404		};
405
406		lpi2c3: i2c@403f8000 {
407			compatible = "nxp,imx-lpi2c";
408			clock-frequency = <I2C_BITRATE_STANDARD>;
409			#address-cells = <1>;
410			#size-cells = <0>;
411			reg = <0x403f8000 0x4000>;
412			interrupts = <30 0>;
413			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 10>;
414			status = "disabled";
415		};
416
417		lpi2c4: i2c@403fc000 {
418			compatible = "nxp,imx-lpi2c";
419			clock-frequency = <I2C_BITRATE_STANDARD>;
420			#address-cells = <1>;
421			#size-cells = <0>;
422			reg = <0x403fc000 0x4000>;
423			interrupts = <31 0>;
424			clocks = <&ccm IMX_CCM_LPI2C_CLK 0x80 24>;
425			status = "disabled";
426		};
427
428		iomuxc: iomuxc@401f8000 {
429			compatible = "nxp,imx-iomuxc";
430			reg = <0x401f8000 0x4000>;
431			status = "okay";
432			pinctrl: pinctrl {
433				status = "okay";
434				compatible = "nxp,mcux-rt-pinctrl";
435			};
436		};
437
438		lcdif: display-controller@402b8000 {
439			compatible = "nxp,imx-elcdif";
440			reg = <0x402b8000 0x4000>;
441			interrupts = <42 0>;
442			status = "disabled";
443			nxp,pxp = <&pxp>;
444		};
445
446		lpspi1: spi@40394000 {
447			compatible = "nxp,imx-lpspi";
448			reg = <0x40394000 0x4000>;
449			interrupts = <32 3>;
450			status = "disabled";
451			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 0>;
452			#address-cells = <1>;
453			#size-cells = <0>;
454		};
455
456		lpspi2: spi@40398000 {
457			compatible = "nxp,imx-lpspi";
458			reg = <0x40398000 0x4000>;
459			interrupts = <33 3>;
460			status = "disabled";
461			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 2>;
462			#address-cells = <1>;
463			#size-cells = <0>;
464		};
465
466		lpspi3: spi@4039c000 {
467			compatible = "nxp,imx-lpspi";
468			reg = <0x4039c000 0x4000>;
469			interrupts = <34 3>;
470			status = "disabled";
471			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 4>;
472			#address-cells = <1>;
473			#size-cells = <0>;
474		};
475
476		lpspi4: spi@403a0000 {
477			compatible = "nxp,imx-lpspi";
478			reg = <0x403a0000 0x4000>;
479			interrupts = <35 3>;
480			status = "disabled";
481			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 6>;
482			#address-cells = <1>;
483			#size-cells = <0>;
484		};
485
486		lpuart1: uart@40184000 {
487			compatible = "nxp,kinetis-lpuart";
488			reg = <0x40184000 0x4000>;
489			interrupts = <20 0>;
490			clocks = <&ccm IMX_CCM_LPUART_CLK 0x7c 24>;
491			dmas = <&edma0 1 2>, <&edma0 2 3>;
492			dma-names = "tx", "rx";
493			status = "disabled";
494		};
495
496		lpuart2: uart@40188000 {
497			compatible = "nxp,kinetis-lpuart";
498			reg = <0x40188000 0x4000>;
499			interrupts = <21 0>;
500			clocks = <&ccm IMX_CCM_LPUART_CLK 0x68 28>;
501			dmas = <&edma0 3 66>, <&edma0 4 67>;
502			dma-names = "tx", "rx";
503			status = "disabled";
504		};
505
506		lpuart3: uart@4018c000 {
507			compatible = "nxp,kinetis-lpuart";
508			reg = <0x4018c000 0x4000>;
509			interrupts = <22 0>;
510			clocks = <&ccm IMX_CCM_LPUART_CLK 0x68 12>;
511			dmas = <&edma0 5 4>, <&edma0 6 5>;
512			dma-names = "tx", "rx";
513			status = "disabled";
514		};
515
516		lpuart4: uart@40190000 {
517			compatible = "nxp,kinetis-lpuart";
518			reg = <0x40190000 0x4000>;
519			interrupts = <23 0>;
520			clocks = <&ccm IMX_CCM_LPUART_CLK 0x6c 24>;
521			dmas = <&edma0 7 68>, <&edma0 8 69>;
522			dma-names = "tx", "rx";
523			status = "disabled";
524		};
525
526		lpuart5: uart@40194000 {
527			compatible = "nxp,kinetis-lpuart";
528			reg = <0x40194000 0x4000>;
529			interrupts = <24 0>;
530			clocks = <&ccm IMX_CCM_LPUART_CLK 0x74 2>;
531			dmas = <&edma0 9 6>, <&edma0 10 7>;
532			dma-names = "tx", "rx";
533			status = "disabled";
534		};
535
536		lpuart6: uart@40198000 {
537			compatible = "nxp,kinetis-lpuart";
538			reg = <0x40198000 0x4000>;
539			interrupts = <25 0>;
540			clocks = <&ccm IMX_CCM_LPUART_CLK 0x74 6>;
541			dmas = <&edma0 11 70>, <&edma0 12 71>;
542			dma-names = "tx", "rx";
543			status = "disabled";
544		};
545
546		lpuart7: uart@4019c000 {
547			compatible = "nxp,kinetis-lpuart";
548			reg = <0x4019c000 0x4000>;
549			interrupts = <26 0>;
550			clocks = <&ccm IMX_CCM_LPUART_CLK 0x7c 26>;
551			dmas = <&edma0 13 8>, <&edma0 14 9>;
552			dma-names = "tx", "rx";
553			status = "disabled";
554		};
555
556		lpuart8: uart@401a0000 {
557			compatible = "nxp,kinetis-lpuart";
558			reg = <0x401a0000 0x4000>;
559			interrupts = <27 0>;
560			clocks = <&ccm IMX_CCM_LPUART_CLK 0x80 14>;
561			dmas = <&edma0 15 72>, <&edma0 16 73>;
562			dma-names = "tx", "rx";
563			status = "disabled";
564		};
565
566		adc1: adc@400c4000 {
567			compatible = "nxp,mcux-12b1msps-sar";
568			reg = <0x400C4000 0x1000>;
569			interrupts = <67 0>;
570			clk-divider = <1>;
571			sample-period-mode = <0>;
572			status = "disabled";
573			#io-channel-cells = <1>;
574		};
575
576		adc2: adc@400c8000 {
577			compatible = "nxp,mcux-12b1msps-sar";
578			reg = <0x400C8000 0x1000>;
579			interrupts = <68 0>;
580			clk-divider = <1>;
581			sample-period-mode = <0>;
582			status = "disabled";
583			#io-channel-cells = <1>;
584		};
585
586		flexpwm1: flexpwm@403dc000 {
587			compatible = "nxp,flexpwm";
588			reg = <0x403dc000 0x4000>;
589			interrupts = <106 0>;
590
591			flexpwm1_pwm0: flexpwm1_pwm0 {
592				compatible = "nxp,imx-pwm";
593				index = <0>;
594				interrupts = <102 0>;
595				#pwm-cells = <3>;
596				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
597				nxp,prescaler = <128>;
598				status = "disabled";
599			};
600
601			flexpwm1_pwm1: flexpwm1_pwm1 {
602				compatible = "nxp,imx-pwm";
603				index = <1>;
604				interrupts = <103 0>;
605				#pwm-cells = <3>;
606				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
607				nxp,prescaler = <128>;
608				status = "disabled";
609			};
610
611			flexpwm1_pwm2: flexpwm1_pwm2 {
612				compatible = "nxp,imx-pwm";
613				index = <2>;
614				interrupts = <104 0>;
615				#pwm-cells = <3>;
616				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
617				nxp,prescaler = <128>;
618				status = "disabled";
619			};
620
621			flexpwm1_pwm3: flexpwm1_pwm3 {
622				compatible = "nxp,imx-pwm";
623				index = <3>;
624				interrupts = <105 0>;
625				#pwm-cells = <3>;
626				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
627				nxp,prescaler = <128>;
628				status = "disabled";
629			};
630		};
631
632		flexpwm2: flexpwm@403e0000 {
633			compatible = "nxp,flexpwm";
634			reg = <0x403e0000 0x4000>;
635			interrupts =  <141 0>;
636
637			flexpwm2_pwm0: flexpwm2_pwm0 {
638				compatible = "nxp,imx-pwm";
639				index = <0>;
640				interrupts = <137 0>;
641				#pwm-cells = <3>;
642				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
643				nxp,prescaler = <128>;
644				status = "disabled";
645			};
646
647			flexpwm2_pwm1: flexpwm2_pwm1 {
648				compatible = "nxp,imx-pwm";
649				index = <1>;
650				interrupts = <138 0>;
651				#pwm-cells = <3>;
652				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
653				nxp,prescaler = <128>;
654				status = "disabled";
655			};
656
657			flexpwm2_pwm2: flexpwm2_pwm2 {
658				compatible = "nxp,imx-pwm";
659				index = <2>;
660				interrupts = <139 0>;
661				#pwm-cells = <3>;
662				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
663				nxp,prescaler = <128>;
664				status = "disabled";
665			};
666
667			flexpwm2_pwm3: flexpwm2_pwm3 {
668				compatible = "nxp,imx-pwm";
669				index = <3>;
670				interrupts = <140 0>;
671				#pwm-cells = <3>;
672				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
673				nxp,prescaler = <128>;
674				status = "disabled";
675			};
676		};
677
678		flexpwm3: flexpwm@403e4000 {
679			compatible = "nxp,flexpwm";
680			reg = <0x403e4000 0x4000>;
681			interrupts =  <146 0>;
682
683			flexpwm3_pwm0: flexpwm3_pwm0 {
684				compatible = "nxp,imx-pwm";
685				index = <0>;
686				interrupts = <142 0>;
687				#pwm-cells = <3>;
688				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
689				nxp,prescaler = <128>;
690				status = "disabled";
691			};
692
693			flexpwm3_pwm1: flexpwm3_pwm1 {
694				compatible = "nxp,imx-pwm";
695				index = <1>;
696				interrupts = <143 0>;
697				#pwm-cells = <3>;
698				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
699				nxp,prescaler = <128>;
700				status = "disabled";
701			};
702
703			flexpwm3_pwm2: flexpwm3_pwm2 {
704				compatible = "nxp,imx-pwm";
705				index = <2>;
706				interrupts = <144 0>;
707				#pwm-cells = <3>;
708				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
709				nxp,prescaler = <128>;
710				status = "disabled";
711			};
712
713			flexpwm3_pwm3: flexpwm3_pwm3 {
714				compatible = "nxp,imx-pwm";
715				index = <3>;
716				interrupts = <145 0>;
717				#pwm-cells = <3>;
718				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
719				nxp,prescaler = <128>;
720				status = "disabled";
721			};
722		};
723
724		flexpwm4: flexpwm@403e8000 {
725			compatible = "nxp,flexpwm";
726			reg = <0x403e8000 0x4000>;
727			interrupts = <151 0>;
728
729			flexpwm4_pwm0: flexpwm4_pwm0 {
730				compatible = "nxp,imx-pwm";
731				index = <0>;
732				interrupts = <147 0>;
733				#pwm-cells = <3>;
734				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
735				nxp,prescaler = <128>;
736				status = "disabled";
737			};
738
739			flexpwm4_pwm1: flexpwm4_pwm1 {
740				compatible = "nxp,imx-pwm";
741				index = <1>;
742				interrupts = <148 0>;
743				#pwm-cells = <3>;
744				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
745				nxp,prescaler = <128>;
746				status = "disabled";
747			};
748
749			flexpwm4_pwm2: flexpwm4_pwm2 {
750				compatible = "nxp,imx-pwm";
751				index = <2>;
752				interrupts = <149 0>;
753				#pwm-cells = <3>;
754				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
755				nxp,prescaler = <128>;
756				status = "disabled";
757			};
758
759			flexpwm4_pwm3: flexpwm4_pwm3 {
760				compatible = "nxp,imx-pwm";
761				index = <3>;
762				interrupts = <150 0>;
763				#pwm-cells = <3>;
764				clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
765				nxp,prescaler = <128>;
766				status = "disabled";
767			};
768		};
769
770		enet: ethernet@402d8000 {
771			compatible = "nxp,kinetis-ethernet";
772			reg = <0x402D8000 0x628>;
773			interrupts = <114 0>;
774			interrupt-names = "COMMON";
775			status = "disabled";
776			phy-addr = <0>;
777			ptp: ptp {
778				compatible = "nxp,kinetis-ptp";
779				status = "disabled";
780				interrupts = <115 0>;
781				interrupt-names = "IEEE1588_TMR";
782			};
783		};
784
785		src: reset-controller@400f8000 {
786			compatible = "nxp,imx-src";
787			reg = <0x400f8000 0x4000>;
788			status = "okay";
789		};
790
791		trng: random@400cc000 {
792			compatible = "nxp,kinetis-trng";
793			reg = <0x400cc000 0x4000>;
794			status = "okay";
795			interrupts = <53 0>;
796		};
797
798		usb1: usbd@402e0000 {
799			compatible = "nxp,ehci";
800			reg = <0x402E0000 0x200>;
801			interrupts = <113 1>;
802			interrupt-names = "usb_otg";
803			clocks = <&usbclk>;
804			num-bidir-endpoints = <8>;
805			status = "disabled";
806		};
807
808		usb2: usbd@402e0200 {
809			compatible = "nxp,ehci";
810			reg = <0x402E0200 0x200>;
811			interrupts = <112 1>;
812			interrupt-names = "usb_otg";
813			clocks = <&usbclk>;
814			num-bidir-endpoints = <8>;
815			status = "disabled";
816		};
817
818		usdhc1: usdhc@402c0000 {
819			compatible = "nxp,imx-usdhc";
820			reg = <0x402c0000 0x4000>;
821			status = "disabled";
822			interrupts = <110 0>;
823			clocks = <&ccm IMX_CCM_USDHC1_CLK 0 0>;
824			max-current-330 = <1020>;
825			max-current-180 = <1020>;
826			max-bus-freq = <208000000>;
827			min-bus-freq = <400000>;
828		};
829
830		usdhc2: usdhc@402c4000 {
831			compatible = "nxp,imx-usdhc";
832			reg = <0x402c4000 0x4000>;
833			status = "disabled";
834			interrupts = <111 0>;
835			clocks = <&ccm IMX_CCM_USDHC2_CLK 0 0>;
836			max-current-330 = <120>;
837			max-current-180 = <45>;
838			max-bus-freq = <198000000>;
839			min-bus-freq = <400000>;
840		};
841
842		csi: csi@402bc000 {
843			compatible = "nxp,imx-csi";
844			reg = <0x402BC000 0x4000>;
845			interrupts = <43 1>;
846			status = "disabled";
847		};
848
849		edma0: dma-controller@400e8000 {
850			#dma-cells = <2>;
851			compatible = "nxp,mcux-edma";
852			dma-channels = <32>;
853			dma-requests = <128>;
854			nxp,mem2mem;
855			nxp,a_on;
856			reg = <0x400E8000 0x4000>,
857				<0x400EC000 0x4000>;
858			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
859				<4 0>, <5 0>, <6 0>, <7 0>,
860				<8 0>, <9 0>, <10 0>, <11 0>,
861				<12 0>, <13 0>, <14 0>, <15 0>,
862				<16 0>;
863			irq-shared-offset = <16>;
864			clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
865			status = "disabled";
866		};
867
868		flexcan1: can@401d0000 {
869			compatible = "nxp,flexcan";
870			reg = <0x401d0000 0x1000>;
871			interrupts = <36 0>;
872			interrupt-names = "common";
873			clocks = <&ccm IMX_CCM_CAN_CLK 0x68 14>;
874			clk-source = <2>;
875			sample-point = <875>;
876			status = "disabled";
877		};
878
879		flexcan2: can@401d4000 {
880			compatible = "nxp,flexcan";
881			reg = <0x401d4000 0x1000>;
882			interrupts = <37 0>;
883			interrupt-names = "common";
884			clocks = <&ccm IMX_CCM_CAN_CLK 0x68 18>;
885			clk-source = <2>;
886			sample-point = <875>;
887			status = "disabled";
888		};
889
890		flexcan3: can@401d8000 {
891			compatible = "nxp,flexcan-fd", "nxp,flexcan";
892			reg = <0x401d8000 0x1000>;
893			interrupts = <154 0>;
894			interrupt-names = "common";
895			clocks = <&ccm IMX_CCM_CAN_CLK 0x84 6>;
896			clk-source = <2>;
897			sample-point = <875>;
898			sample-point-data = <875>;
899			status = "disabled";
900		};
901
902		wdog0: wdog@400b8000 {
903			compatible = "nxp,imx-wdog";
904			reg = <0x400b8000 0xA>;
905			status = "disabled";
906			interrupts = <92 0>;
907		};
908
909		wdog1: wdog@400d0000 {
910			compatible = "nxp,imx-wdog";
911			reg = <0x400d0000 0xA>;
912			status = "disabled";
913			interrupts = <45 0>;
914		};
915
916		anatop: anatop@400d8000 {
917			compatible = "nxp,imx-anatop";
918			reg = <0x400d8000 0x4000>;
919			#clock-cells = <4>;
920			#pll-clock-cells = <3>;
921		};
922
923		iomuxcgpr: iomuxcgpr@400ac000 {
924			compatible = "nxp,imx-gpr";
925			reg = <0x400AC000 0x4000>;
926			#pinmux-cells = <2>;
927		};
928
929		pxp: pxp@402b4000 {
930			compatible = "nxp,pxp";
931			reg = <0x402b4000 0x4000>;
932			interrupts = <44 0>;
933			status = "disabled";
934			#dma-cells = <0>;
935		};
936
937		sai1: sai@40384000 {
938			compatible = "nxp,mcux-i2s";
939			#address-cells = <1>;
940			#size-cells = <0>;
941			#pinmux-cells = <2>;
942			reg = <0x40384000 0x4000>;
943			clocks = <&ccm IMX_CCM_SAI1_CLK 0x7C 18>;
944			/* Source clock from Audio PLL */
945			clock-mux = <2>;
946			/* Audio PLL Output Frequency is determined by:
947			 * (Fref * (DIV_SELECT + NUM/DENOM)) / POST_DIV
948			 * = (24MHz * (32 + 77 / 100)) / 1 = 786.48 MHz
949			 */
950			pll-clocks = <&anatop 0x70 0xC000 0>,
951				      <&anatop 0x70 0x7F 32>,
952				      <&anatop 0x70 0x180000 1>,
953				      <&anatop 0x80 0x3FFFFFFF 77>,
954				      <&anatop 0x90 0x3FFFFFFF 100>;
955			pll-clock-names = "src", "lp", "pd", "num", "den";
956			/* The maximum input frequency into the SAI mclk input is 300MHz
957			 * Based on this requirement, pre-div must be at least 3
958			 * The pre-div and post-div are one less than the actual divide-by amount.
959			 * A pre-div value of 0x1 results in a pre-divider of
960			 * (1+1) = 2
961			 */
962			pre-div = <0x3>;
963			podf = <0x0F>;
964			pinmuxes = <&iomuxcgpr 0x4 0x80000>;
965			interrupts = <56 0>;
966			dmas = <&edma0 0 19>, <&edma0 0 20>;
967			dma-names = "rx", "tx";
968			/* This translates to SAIChannelMask (fsl_sai.c) and
969			 * cannot be 0
970			 */
971			nxp,tx-channel = <1>;
972			nxp,tx-dma-channel = <0>;
973			nxp,rx-dma-channel = <1>;
974			status = "disabled";
975		};
976
977		sai2: sai@40388000 {
978			compatible = "nxp,mcux-i2s";
979			#address-cells = <1>;
980			#size-cells = <0>;
981			#pinmux-cells = <2>;
982			reg = <0x40388000 0x4000>;
983			clocks = <&ccm IMX_CCM_SAI2_CLK 0x7C 20>;
984			/* Source clock from Audio PLL */
985			clock-mux = <2>;
986			pre-div = <0>;
987			podf = <63>;
988			pll-clocks = <&anatop 0x70 0xC000 0x0>,
989					<&anatop 0x70 0x7F 32>,
990					<&anatop 0x70 0x180000 1>,
991					<&anatop 0x80 0x3FFFFFFF 77>,
992					<&anatop 0x90 0x3FFFFFFF 100>;
993			pll-clock-names = "src", "lp", "pd", "num", "den";
994			pinmuxes = <&iomuxcgpr 0x4 0x100000>;
995			interrupts = <57 0>;
996			dmas = <&edma0 0 21>, <&edma0 0 22>;
997			dma-names = "rx", "tx";
998			nxp,tx-channel = <0>;
999			nxp,tx-dma-channel = <3>;
1000			nxp,rx-dma-channel = <4>;
1001			status = "disabled";
1002		};
1003
1004		sai3: sai@4038c000 {
1005			compatible = "nxp,mcux-i2s";
1006			#address-cells = <1>;
1007			#size-cells = <0>;
1008			#pinmux-cells = <2>;
1009			reg = <0x4038C000 0x4000>;
1010			clocks = <&ccm IMX_CCM_SAI3_CLK 0x7C 22>;
1011			/* Source clock from Audio PLL */
1012			clock-mux = <2>;
1013			pre-div = <0>;
1014			podf = <63>;
1015			pll-clocks = <&anatop 0x70 0xC000 0>,
1016				   <&anatop 0x70 0x7F 32>,
1017				   <&anatop 0x70 0x180000 1>,
1018				   <&anatop 0x80 0x3FFFFFFF 77>,
1019				   <&anatop 0x90 0x3FFFFFFF 100>;
1020			pll-clock-names = "src", "lp", "pd", "num", "den";
1021			pinmuxes = <&iomuxcgpr 0x4 0x200000>;
1022			interrupts = <58 0>, <59 0>;
1023			dmas = <&edma0 0 83>, <&edma0 0 84>;
1024			dma-names = "rx", "tx";
1025			nxp,tx-channel = <0>;
1026			nxp,tx-dma-channel = <5>;
1027			nxp,rx-dma-channel = <6>;
1028			status = "disabled";
1029		};
1030
1031		qdec1: qdec@403c8000 {
1032			compatible = "nxp,mcux-qdec";
1033			reg = <0x403c8000 0x4000>;
1034			interrupts = <129 0>;
1035			status = "disabled";
1036		};
1037
1038		qdec2: qdec@403cc000 {
1039			compatible = "nxp,mcux-qdec";
1040			reg = <0x403cc000 0x4000>;
1041			interrupts = <130 0>;
1042			status = "disabled";
1043		};
1044
1045		qdec3: qdec@403d0000 {
1046			compatible = "nxp,mcux-qdec";
1047			reg = <0x403d0000 0x4000>;
1048			interrupts = <131 0>;
1049			status = "disabled";
1050		};
1051
1052		qdec4: qdec@403d4000 {
1053			compatible = "nxp,mcux-qdec";
1054			reg = <0x403d4000 0x4000>;
1055			interrupts = <132 0>;
1056			status = "disabled";
1057		};
1058
1059		xbar1: xbar1@403bc000 {
1060			compatible = "nxp,mcux-xbar";
1061			reg = <0x403bc000 0x4000>;
1062			interrupts = <116 0>, <117 0>;
1063			status = "disabled";
1064		};
1065
1066		xbar2: xbar2@403c0000 {
1067			compatible = "nxp,mcux-xbar";
1068			reg = <0x403c0000 0x4000>;
1069			status = "disabled";
1070		};
1071
1072		xbar3: xbar3@403c4000 {
1073			compatible = "nxp,mcux-xbar";
1074			reg = <0x403c4000 0x4000>;
1075			status = "disabled";
1076		};
1077
1078		dcp: dcp@402fc000 {
1079			compatible = "nxp,mcux-dcp";
1080			reg = <0x402fc000 0x4000>;
1081			interrupts = <50 0>, <51 0>;
1082			status = "okay";
1083		};
1084
1085		tempmon: tempmon@400d8000 {
1086			compatible = "nxp,tempmon";
1087			reg = <0x400d8000 0x2a0>;
1088			status = "disabled";
1089		};
1090	};
1091};
1092
1093&nvic {
1094	arm,num-irq-priority-bits = <4>;
1095};
1096
1097&systick {
1098	/*
1099	 * RT10xx relies by default on the GPT Timer for system clock
1100	 * implementation, so the SysTick node should not be enabled.
1101	 */
1102	status = "disabled";
1103};
1104