1/*
2 * Copyright (c) 2022 Microchip Technology Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8
9#include <zephyr/dt-bindings/i2c/i2c.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
12#include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
13
14#include "mec172x/mec172x-vw-routing.dtsi"
15
16#include <mem.h>
17#include <freq.h>
18
19/ {
20	cpus {
21		#address-cells = <1>;
22		#size-cells = <0>;
23
24		cpu0: cpu@0 {
25			device_type = "cpu";
26			compatible = "arm,cortex-m4";
27			reg = <0>;
28			cpu-power-states = <&idle &suspend_to_ram>;
29		};
30
31		power-states {
32			idle: idle {
33				compatible = "zephyr,power-state";
34				power-state-name = "suspend-to-idle";
35				min-residency-us = <1000000>;
36			};
37
38			suspend_to_ram: suspend_to_ram {
39				compatible = "zephyr,power-state";
40				power-state-name = "suspend-to-ram";
41				min-residency-us = <2000000>;
42			};
43		};
44	};
45
46	flash0: flash@c0000 {
47		reg = <0x000C0000 0x58000>;
48	};
49
50	flash1: flash@60000000 {
51		reg = <0x60000000 0x80000>;
52	};
53
54	sram0: memory@118000 {
55		compatible = "mmio-sram";
56		reg = <0x00118000 0x10000>;
57	};
58
59	soc {
60		#include "mec172x_common.dtsi"
61	};
62
63};
64
65&spi0 {
66	status = "okay";
67	clock-frequency = <12000000>;
68	lines = <2>;
69	chip-select = <0>;
70	pinctrl-0 = < &gpspi_cs_n_gpio116
71		      &gpspi_clk_gpio117
72		      &gpspi_io0_gpio074
73		      &gpspi_io1_gpio075
74		      &gpspi_wp_n_gpio076 >;
75	pinctrl-names = "default";
76
77	int_flash: sst25pf040@0 {
78		compatible ="jedec,spi-nor";
79		/* 4 Mbit Flash */
80		size = <DT_SIZE_M(4)>;
81		reg = <0>;
82		spi-max-frequency = <DT_FREQ_M(40)>;
83		status = "okay";
84		jedec-id = [62 06 13];
85	};
86};
87
88&nvic {
89	arm,num-irq-priority-bits = <3>;
90};
91
92&systick {
93	status = "disabled";
94};
95
96#include "mec172x/mec172xnsz-pinctrl.dtsi"
97
98&gpspi_wp_n_gpio076 {
99	output-high;
100};
101