1/*
2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8#include <zephyr/dt-bindings/gpio/gpio.h>
9#include <zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h>
10#include "psoc6_01.dtsi"
11
12/ {
13	soc {
14		/delete-node/ gpio@40320080; // gpio_prt1
15		/delete-node/ gpio@40320100; // gpio_prt2
16		/delete-node/ gpio@40320180; // gpio_prt3
17		/delete-node/ gpio@40320200; // gpio_prt4
18		/delete-node/ gpio@40320400; // gpio_prt8
19		/delete-node/ gpio@40320580; // gpio_prt11
20		/delete-node/ gpio@40320680; // gpio_prt13
21		/delete-node/ gpio@40320700; // gpio_prt14
22
23		pinctrl: pinctrl@40310000 {
24			/* scb_i2c_scl */
25			/omit-if-no-ref/ p5_0_scb5_i2c_scl: p5_0_scb5_i2c_scl {
26				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_7)>;
27			};
28			/omit-if-no-ref/ p6_4_scb6_i2c_scl: p6_4_scb6_i2c_scl {
29				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_7)>;
30			};
31			/omit-if-no-ref/ p6_4_scb8_i2c_scl: p6_4_scb8_i2c_scl {
32				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_DS_2)>;
33			};
34			/omit-if-no-ref/ p9_0_scb2_i2c_scl: p9_0_scb2_i2c_scl {
35				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_7)>;
36			};
37			/omit-if-no-ref/ p10_0_scb1_i2c_scl: p10_0_scb1_i2c_scl {
38				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_7)>;
39			};
40
41			/* scb_i2c_sda */
42			/omit-if-no-ref/ p5_1_scb5_i2c_sda: p5_1_scb5_i2c_sda {
43				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_7)>;
44			};
45			/omit-if-no-ref/ p6_5_scb6_i2c_sda: p6_5_scb6_i2c_sda {
46				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_7)>;
47			};
48			/omit-if-no-ref/ p6_5_scb8_i2c_sda: p6_5_scb8_i2c_sda {
49				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_DS_2)>;
50			};
51			/omit-if-no-ref/ p7_1_scb4_i2c_sda: p7_1_scb4_i2c_sda {
52				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_7)>;
53			};
54			/omit-if-no-ref/ p9_1_scb2_i2c_sda: p9_1_scb2_i2c_sda {
55				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_7)>;
56			};
57			/omit-if-no-ref/ p10_1_scb1_i2c_sda: p10_1_scb1_i2c_sda {
58				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_7)>;
59			};
60
61			/* scb_uart_cts */
62			/omit-if-no-ref/ p0_5_scb0_uart_cts: p0_5_scb0_uart_cts {
63				pinmux = <DT_CAT1_PINMUX(0, 5, HSIOM_SEL_ACT_6)>;
64			};
65			/omit-if-no-ref/ p5_3_scb5_uart_cts: p5_3_scb5_uart_cts {
66				pinmux = <DT_CAT1_PINMUX(5, 3, HSIOM_SEL_ACT_6)>;
67			};
68			/omit-if-no-ref/ p6_3_scb3_uart_cts: p6_3_scb3_uart_cts {
69				pinmux = <DT_CAT1_PINMUX(6, 3, HSIOM_SEL_ACT_6)>;
70			};
71			/omit-if-no-ref/ p6_7_scb6_uart_cts: p6_7_scb6_uart_cts {
72				pinmux = <DT_CAT1_PINMUX(6, 7, HSIOM_SEL_ACT_6)>;
73			};
74			/omit-if-no-ref/ p9_3_scb2_uart_cts: p9_3_scb2_uart_cts {
75				pinmux = <DT_CAT1_PINMUX(9, 3, HSIOM_SEL_ACT_6)>;
76			};
77			/omit-if-no-ref/ p10_3_scb1_uart_cts: p10_3_scb1_uart_cts {
78				pinmux = <DT_CAT1_PINMUX(10, 3, HSIOM_SEL_ACT_6)>;
79			};
80
81			/* scb_uart_rts */
82			/omit-if-no-ref/ p0_4_scb0_uart_rts: p0_4_scb0_uart_rts {
83				pinmux = <DT_CAT1_PINMUX(0, 4, HSIOM_SEL_ACT_6)>;
84			};
85			/omit-if-no-ref/ p5_2_scb5_uart_rts: p5_2_scb5_uart_rts {
86				pinmux = <DT_CAT1_PINMUX(5, 2, HSIOM_SEL_ACT_6)>;
87			};
88			/omit-if-no-ref/ p6_2_scb3_uart_rts: p6_2_scb3_uart_rts {
89				pinmux = <DT_CAT1_PINMUX(6, 2, HSIOM_SEL_ACT_6)>;
90			};
91			/omit-if-no-ref/ p6_6_scb6_uart_rts: p6_6_scb6_uart_rts {
92				pinmux = <DT_CAT1_PINMUX(6, 6, HSIOM_SEL_ACT_6)>;
93			};
94			/omit-if-no-ref/ p7_2_scb4_uart_rts: p7_2_scb4_uart_rts {
95				pinmux = <DT_CAT1_PINMUX(7, 2, HSIOM_SEL_ACT_6)>;
96			};
97			/omit-if-no-ref/ p9_2_scb2_uart_rts: p9_2_scb2_uart_rts {
98				pinmux = <DT_CAT1_PINMUX(9, 2, HSIOM_SEL_ACT_6)>;
99			};
100			/omit-if-no-ref/ p10_2_scb1_uart_rts: p10_2_scb1_uart_rts {
101				pinmux = <DT_CAT1_PINMUX(10, 2, HSIOM_SEL_ACT_6)>;
102			};
103
104			/* scb_uart_rx */
105			/omit-if-no-ref/ p5_0_scb5_uart_rx: p5_0_scb5_uart_rx {
106				pinmux = <DT_CAT1_PINMUX(5, 0, HSIOM_SEL_ACT_6)>;
107			};
108			/omit-if-no-ref/ p6_4_scb6_uart_rx: p6_4_scb6_uart_rx {
109				pinmux = <DT_CAT1_PINMUX(6, 4, HSIOM_SEL_ACT_6)>;
110			};
111			/omit-if-no-ref/ p9_0_scb2_uart_rx: p9_0_scb2_uart_rx {
112				pinmux = <DT_CAT1_PINMUX(9, 0, HSIOM_SEL_ACT_6)>;
113			};
114			/omit-if-no-ref/ p10_0_scb1_uart_rx: p10_0_scb1_uart_rx {
115				pinmux = <DT_CAT1_PINMUX(10, 0, HSIOM_SEL_ACT_6)>;
116			};
117
118			/* scb_uart_tx */
119			/omit-if-no-ref/ p5_1_scb5_uart_tx: p5_1_scb5_uart_tx {
120				pinmux = <DT_CAT1_PINMUX(5, 1, HSIOM_SEL_ACT_6)>;
121			};
122			/omit-if-no-ref/ p6_5_scb6_uart_tx: p6_5_scb6_uart_tx {
123				pinmux = <DT_CAT1_PINMUX(6, 5, HSIOM_SEL_ACT_6)>;
124			};
125			/omit-if-no-ref/ p7_1_scb4_uart_tx: p7_1_scb4_uart_tx {
126				pinmux = <DT_CAT1_PINMUX(7, 1, HSIOM_SEL_ACT_6)>;
127			};
128			/omit-if-no-ref/ p9_1_scb2_uart_tx: p9_1_scb2_uart_tx {
129				pinmux = <DT_CAT1_PINMUX(9, 1, HSIOM_SEL_ACT_6)>;
130			};
131			/omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx {
132				pinmux = <DT_CAT1_PINMUX(10, 1, HSIOM_SEL_ACT_6)>;
133			};
134
135		};
136	};
137};
138