1/*
2 * Copyright (c) 2021 BrainCo Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <freq.h>
8#include <gd/gd32f4xx/gd32f4xx.dtsi>
9
10/ {
11	soc {
12		spi3: spi@40013400 {
13			compatible = "gd,gd32-spi";
14			reg = <0x40013400 0x400>;
15			interrupts = <84 0>;
16			clocks = <&cctl GD32_CLOCK_SPI3>;
17			resets = <&rctl GD32_RESET_SPI3>;
18			status = "disabled";
19			#address-cells = <1>;
20			#size-cells = <0>;
21		};
22
23		spi4: spi@40015000 {
24			compatible = "gd,gd32-spi";
25			reg = <0x40015000 0x400>;
26			interrupts = <85 0>;
27			clocks = <&cctl GD32_CLOCK_SPI4>;
28			resets = <&rctl GD32_RESET_SPI4>;
29			status = "disabled";
30			#address-cells = <1>;
31			#size-cells = <0>;
32		};
33
34		spi5: spi@40015400 {
35			compatible = "gd,gd32-spi";
36			reg = <0x40015400 0x400>;
37			interrupts = <86 0>;
38			clocks = <&cctl GD32_CLOCK_SPI5>;
39			resets = <&rctl GD32_RESET_SPI5>;
40			status = "disabled";
41			#address-cells = <1>;
42			#size-cells = <0>;
43		};
44	};
45};
46
47&cpu0 {
48	clock-frequency = <DT_FREQ_M(200)>;
49};
50