1/* SPDX-License-Identifier: Apache-2.0 */
2
3#include <arm/armv7-m.dtsi>
4#include <mem.h>
5#include <freq.h>
6#include <zephyr/dt-bindings/i2c/i2c.h>
7#include <zephyr/dt-bindings/gpio/gpio.h>
8
9/ {
10	clocks {
11		uartclk: apb-pclk {
12			compatible = "fixed-clock";
13			clock-frequency = <DT_FREQ_M(24)>;
14			#clock-cells = <0>;
15		};
16		xo32m: xo32m {
17			compatible = "ambiq,clkctrl";
18			clock-frequency = <DT_FREQ_M(32)>;
19			#clock-cells = <1>;
20		};
21		xo32k: xo32k {
22			compatible = "ambiq,clkctrl";
23			clock-frequency = <DT_FREQ_K(32)>;
24			#clock-cells = <1>;
25		};
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu0: cpu@0 {
33			compatible = "arm,cortex-m4f";
34			reg = <0>;
35		};
36	};
37
38	/* TCM */
39	tcm: tcm@10000000 {
40		compatible = "zephyr,memory-region";
41		reg = <0x10000000 0x10000>;
42		zephyr,memory-region = "ITCM";
43	};
44
45	/* SRAM */
46	sram0: memory@10010000 {
47		compatible = "mmio-sram";
48		reg = <0x10010000 0x2B0000>;
49	};
50
51	soc {
52		compatible = "ambiq,apollo4p-blue", "ambiq,apollo4x", "simple-bus";
53
54		flash: flash-controller@18000 {
55			compatible = "ambiq,flash-controller";
56			reg = <0x00018000 0x1e8000>;
57
58			#address-cells = <1>;
59			#size-cells = <1>;
60
61			/* MRAM region */
62			flash0: flash@18000 {
63				compatible = "soc-nv-flash";
64				reg = <0x00018000 0x1e8000>;
65			};
66		};
67
68		pwrcfg: pwrcfg@40021000 {
69			compatible = "ambiq,pwrctrl";
70			reg = <0x40021000 0x400>;
71			#pwrcfg-cells = <2>;
72		};
73
74		stimer0: stimer@40008800 {
75			compatible = "ambiq,stimer";
76			reg = <0x40008800 0x80>;
77			interrupts = <32 0>;
78			status = "okay";
79		};
80
81		counter0: counter@40008000 {
82			compatible = "ambiq,counter";
83			reg = <0x40008000 0x80>;
84			interrupts = <67 0>;
85			status = "disabled";
86		};
87
88		uart0: uart@4001c000 {
89			compatible = "ambiq,uart", "arm,pl011";
90			reg = <0x4001c000 0x1000>;
91			interrupts = <15 0>;
92			interrupt-names = "UART0";
93			status = "disabled";
94			clocks = <&uartclk>;
95			ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
96		};
97		uart1: uart@4001d000 {
98			compatible = "ambiq,uart", "arm,pl011";
99			reg = <0x4001d000 0x1000>;
100			interrupts = <16 0>;
101			interrupt-names = "UART1";
102			status = "disabled";
103			clocks = <&uartclk>;
104			ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
105		};
106
107		uart2: uart@4001e000 {
108			compatible = "ambiq,uart", "arm,pl011";
109			reg = <0x4001e000 0x1000>;
110			interrupts = <17 0>;
111			interrupt-names = "UART2";
112			status = "disabled";
113			clocks = <&uartclk>;
114			ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
115		};
116
117		uart3: uart@4001f000 {
118			compatible = "ambiq,uart", "arm,pl011";
119			reg = <0x4001f000 0x1000>;
120			interrupts = <18 0>;
121			interrupt-names = "UART3";
122			status = "disabled";
123			clocks = <&uartclk>;
124			ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
125		};
126
127		iom0: iom@40050000 {
128			reg = <0x40050000 0x1000>;
129			#address-cells = <1>;
130			#size-cells = <0>;
131			interrupts = <6 0>;
132			status = "disabled";
133			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
134		};
135
136		iom1: iom@40051000 {
137			reg = <0x40051000 0x1000>;
138			#address-cells = <1>;
139			#size-cells = <0>;
140			interrupts = <7 0>;
141			status = "disabled";
142			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
143		};
144
145		iom2: iom@40052000 {
146			reg = <0x40052000 0x1000>;
147			#address-cells = <1>;
148			#size-cells = <0>;
149			interrupts = <8 0>;
150			status = "disabled";
151			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
152		};
153
154		iom3: iom@40053000 {
155			reg = <0x40053000 0x1000>;
156			#address-cells = <1>;
157			#size-cells = <0>;
158			interrupts = <9 0>;
159			status = "disabled";
160			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
161		};
162
163		iom4: spi@40054000 {
164			/* IOM4 works as SPI and is wired internally for BLE HCI. */
165			compatible = "ambiq,spi";
166			reg = <0x40054000 0x1000>;
167			#address-cells = <1>;
168			#size-cells = <0>;
169			interrupts = <10 0>;
170			cs-gpios = <&gpio32_63 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
171			clock-frequency = <DT_FREQ_M(24)>;
172			status = "disabled";
173			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
174
175			bt-hci@0 {
176				compatible = "ambiq,bt-hci-spi";
177				reg = <0>;
178				irq-gpios = <&gpio32_63 21 GPIO_ACTIVE_HIGH>;
179				reset-gpios = <&gpio32_63 23 GPIO_ACTIVE_LOW>;
180				clkreq-gpios = <&gpio32_63 20 GPIO_ACTIVE_HIGH>;
181			};
182		};
183
184		iom5: iom@40055000 {
185			reg = <0x40055000 0x1000>;
186			#address-cells = <1>;
187			#size-cells = <0>;
188			interrupts = <11 0>;
189			status = "disabled";
190			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
191		};
192
193		iom6: iom@40056000 {
194			reg = <0x40056000 0x1000>;
195			#address-cells = <1>;
196			#size-cells = <0>;
197			interrupts = <12 0>;
198			status = "disabled";
199			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
200		};
201
202		iom7: iom@40057000 {
203			reg = <0x40057000 0x1000>;
204			#address-cells = <1>;
205			#size-cells = <0>;
206			interrupts = <13 0>;
207			status = "disabled";
208			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
209		};
210
211		mspi0: spi@40060000 {
212			compatible = "ambiq,mspi";
213			reg = <0x40060000 0x400>;
214			interrupts = <20 0>;
215			#address-cells = <1>;
216			#size-cells = <0>;
217			status = "disabled";
218			ambiq,pwrcfg = <&pwrcfg 0x4 0x4000>;
219		};
220
221		mspi1: spi@40061000 {
222			compatible = "ambiq,mspi";
223			reg = <0x40061000 0x400>;
224			interrupts = <21 0>;
225			#address-cells = <1>;
226			#size-cells = <0>;
227			status = "disabled";
228			ambiq,pwrcfg = <&pwrcfg 0x4 0x8000>;
229		};
230
231		mspi2: spi@40062000 {
232			compatible = "ambiq,mspi";
233			reg = <0x40062000 0x400>;
234			interrupts = <22 0>;
235			#address-cells = <1>;
236			#size-cells = <0>;
237			status = "disabled";
238			ambiq,pwrcfg = <&pwrcfg 0x4 0x10000>;
239		};
240
241		pinctrl: pin-controller@40010000 {
242			compatible = "ambiq,apollo4-pinctrl";
243			reg = <0x40010000 0x800>;
244			#address-cells = <1>;
245			#size-cells = <0>;
246
247			gpio: gpio@40010000 {
248				compatible = "ambiq,gpio";
249				gpio-map-mask = <0xffffffe0 0xffffffc0>;
250				gpio-map-pass-thru = <0x1f 0x3f>;
251				gpio-map = <
252					0x00 0x0 &gpio0_31 0x0 0x0
253					0x20 0x0 &gpio32_63 0x0 0x0
254					0x40 0x0 &gpio64_95 0x0 0x0
255					0x60 0x0 &gpio96_127 0x0 0x0
256				>;
257				reg = <0x40010000>;
258				#gpio-cells = <2>;
259				#address-cells = <1>;
260				#size-cells = <0>;
261				ranges;
262
263				gpio0_31: gpio0_31@0 {
264					compatible = "ambiq,gpio-bank";
265					gpio-controller;
266					#gpio-cells = <2>;
267					reg = <0>;
268					interrupts = <56 0>;
269					status = "disabled";
270				};
271
272				gpio32_63: gpio32_63@80 {
273					compatible = "ambiq,gpio-bank";
274					gpio-controller;
275					#gpio-cells = <2>;
276					reg = <0x80>;
277					interrupts = <57 0>;
278					status = "disabled";
279				};
280
281				gpio64_95: gpio64_95@100 {
282					compatible = "ambiq,gpio-bank";
283					gpio-controller;
284					#gpio-cells = <2>;
285					reg = <0x100>;
286					interrupts = <58 0>;
287					status = "disabled";
288				};
289
290				gpio96_127: gpio96_127@180 {
291					compatible = "ambiq,gpio-bank";
292					gpio-controller;
293					#gpio-cells = <2>;
294					reg = <0x180>;
295					interrupts = <59 0>;
296					status = "disabled";
297				};
298			};
299		};
300
301		wdt0: watchdog@40024000 {
302			compatible = "ambiq,watchdog";
303			reg = <0x40024000 0x400>;
304			interrupts = <1 0>;
305			clock-frequency = <16>;
306			status = "disabled";
307		};
308
309	};
310};
311
312&nvic {
313	arm,num-irq-priority-bits = <3>;
314};
315