1# Copyright (c) 2023 Intel Corporation
2# SPDX-License-Identifier: Apache-2.0
3
4config ARM_SIP_SVC_HAS_INTEL_SDM_MAILBOX_FIFO
5	bool
6	default y
7	depends on DT_HAS_INTEL_SOCFPGA_AGILEX_SIP_SMC_ENABLED
8	imply ARM_SIP_SVC_HAS_DRIVER
9	help
10	  Support for SDM mailbox fifo in Intel SoC FPGA Agilex via SMC calls.
11
12config ARM_SIP_SVC_EL3_MAILBOX_RESPONSE_SIZE
13	int "Size of response buffer used for ASYNC transactions."
14	default 4096
15	depends on ARM_SIP_SVC_HAS_INTEL_SDM_MAILBOX_FIFO
16	help
17	  Size of response buffer used for ASYNC transactions.For Intel Agilex platform
18	  the maximum size of response buffer size is 4096 and minimum is 4 bytes.
19	  Also it should be multiple of 4 bytes.
20
21config ARM_SIP_SVC_EL3_MAX_ALLOWED_TRANSACTIONS
22	int "Maximum allowable ongoing transactions."
23	default 16
24	depends on ARM_SIP_SVC_HAS_INTEL_SDM_MAILBOX_FIFO
25	help
26	  Allowed number of active transactions in sip_svc subsystem for this driver.
27