1 /*
2 * Copyright (c) 2023 Nordic Semiconductor ASA
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6 #define DT_DRV_COMPAT ti_cc32xx_pinctrl
7
8 #include <zephyr/arch/cpu.h>
9 #include <zephyr/devicetree.h>
10 #include <zephyr/drivers/pinctrl.h>
11 #include <zephyr/dt-bindings/pinctrl/ti-cc32xx-pinctrl.h>
12
13 #define MEM_GPIO_PAD_CONFIG_MSK 0xFFFU
14
15 /* pin to pad mapping (255 indicates invalid pin) */
16 static const uint8_t pin2pad[] = {
17 10U, 11U, 12U, 13U, 14U, 15U, 16U, 17U, 255U, 255U, 18U, 19U, 20U,
18 21U, 22U, 23U, 24U, 40U, 28U, 29U, 25U, 255U, 255U, 255U, 255U, 255U,
19 255U, 255U, 26U, 27U, 255U, 255U, 255U, 255U, 255U, 255U, 255U, 255U, 255U,
20 255U, 255U, 255U, 255U, 255U, 31U, 255U, 255U, 255U, 255U, 0U, 255U, 32U,
21 30U, 255U, 1U, 255U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
22 };
23
pinctrl_configure_pin(pinctrl_soc_pin_t pincfg)24 static int pinctrl_configure_pin(pinctrl_soc_pin_t pincfg)
25 {
26 uint8_t pin;
27
28 pin = (pincfg >> TI_CC32XX_PIN_POS) & TI_CC32XX_PIN_MSK;
29 if ((pin >= ARRAY_SIZE(pin2pad)) || (pin2pad[pin] == 255U)) {
30 return -EINVAL;
31 }
32
33 sys_write32(pincfg & MEM_GPIO_PAD_CONFIG_MSK, DT_INST_REG_ADDR(0) + (pin2pad[pin] << 2U));
34
35 return 0;
36 }
37
pinctrl_configure_pins(const pinctrl_soc_pin_t * pins,uint8_t pin_cnt,uintptr_t reg)38 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
39 {
40 ARG_UNUSED(reg);
41
42 for (uint8_t i = 0U; i < pin_cnt; i++) {
43 int ret;
44
45 ret = pinctrl_configure_pin(pins[i]);
46 if (ret < 0) {
47 return ret;
48 }
49 }
50
51 return 0;
52 }
53
