1 /*
2 * (C) Copyright 2020-2021 SiFive, Inc.
3 * (C) Copyright 2023 Antmicro <www.antmicro.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * Based on implementation of fsbl in:
8 * https://github.com/sifive/freedom-u540-c000-bootloader
9 */
10
11 #define DT_DRV_COMPAT sifive_fu740_c000_ddr
12
13 #include <zephyr/init.h>
14 #include <zephyr/kernel.h>
15 #include <zephyr/device.h>
16 #include <zephyr/logging/log.h>
17
18 #include <soc.h>
19 #include "sifive_ddrregs.h"
20
21 LOG_MODULE_REGISTER(sifive_ddr);
22
23 #define DRAM_CLASS_OFFSET 8
24 #define DRAM_CLASS_DDR4 0xA
25 #define OPTIMAL_RMODW_EN BIT(0)
26 #define DISABLE_RD_INTERLEAVE BIT(16)
27 #define OUT_OF_RANGE BIT(1)
28 #define MULTIPLE_OUT_OF_RANGE BIT(2)
29 #define PORT_COMMAND_CHANNEL_ERROR BIT(7)
30 #define MC_INIT_COMPLETE BIT(8)
31 #define LEVELING_OPERATION_COMPLETED BIT(22)
32 #define DFI_PHY_WRLELV_MODE BIT(24)
33 #define DFI_PHY_RDLVL_MODE BIT(24)
34 #define DFI_PHY_RDLVL_GATE_MODE BIT(0)
35 #define VREF_EN BIT(24)
36 #define PORT_ADDR_PROTECTION_EN BIT(0)
37 #define AXI0_ADDRESS_RANGE_ENABLE BIT(8)
38 #define AXI0_RANGE_PROT_BITS_0 (BIT(24) | BIT(25));
39 #define RDLVL_EN BIT(16)
40 #define RDLVL_GATE_EN BIT(24)
41 #define WRLVL_EN BIT(0)
42
43 #define PHY_RX_CAL_DQ0_0_OFFSET 0
44 #define PHY_RX_CAL_DQ1_0_OFFSET 16
45
46 #define DDR_CTL_REG(d, i) (*(d->ddrctl + i))
47 #define DDR_PHY_REG(d, i) (*(d->ddrphy + i))
48
49 struct ddr_ctrl_data {
50 volatile uint32_t *const ddrctl;
51 volatile uint32_t *const ddrphy;
52 volatile uint32_t *const ddr_physical_filter;
53
54 volatile uint32_t *const ddr_start;
55 const size_t ddr_size;
56 };
57
phy_reset(struct ddr_ctrl_data * ddr_ctrl)58 static inline void phy_reset(struct ddr_ctrl_data *ddr_ctrl)
59 {
60 unsigned int i;
61
62 for (i = 1152; i <= 1214; i++) {
63 DDR_PHY_REG(ddr_ctrl, i) = ddr_phy_settings[i];
64 }
65 for (i = 0; i <= 1151; i++) {
66 DDR_PHY_REG(ddr_ctrl, i) = ddr_phy_settings[i];
67 }
68 }
69
ddr_writeregmap(struct ddr_ctrl_data * ddr_ctrl)70 static inline void ddr_writeregmap(struct ddr_ctrl_data *ddr_ctrl)
71 {
72 unsigned int i;
73
74 for (i = 0; i <= 264; i++) {
75 DDR_CTL_REG(ddr_ctrl, i) = ddr_ctl_settings[i];
76 }
77 phy_reset(ddr_ctrl);
78 }
79
ddr_getdramclass(struct ddr_ctrl_data * ddr_ctrl)80 static inline uint32_t ddr_getdramclass(struct ddr_ctrl_data *ddr_ctrl)
81 {
82 return ((DDR_CTL_REG(ddr_ctrl, 0) >> DRAM_CLASS_OFFSET) & 0xF);
83 }
84
check_errata(uint32_t regbase,uint32_t updownreg)85 static inline void check_errata(uint32_t regbase, uint32_t updownreg)
86 {
87 uint64_t fails = 0;
88 uint32_t bit, dq;
89
90 for (bit = 0, dq = 0; bit < 2; bit++, dq++) {
91 uint32_t phy_rx_cal_dqn_0_offset;
92
93 if (bit == 0) {
94 phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ0_0_OFFSET;
95 } else {
96 phy_rx_cal_dqn_0_offset = PHY_RX_CAL_DQ1_0_OFFSET;
97 }
98
99 uint32_t down = (updownreg >> phy_rx_cal_dqn_0_offset) & 0x3F;
100 uint32_t up = (updownreg >> (phy_rx_cal_dqn_0_offset + 6)) & 0x3F;
101
102 uint8_t failc0 = ((down == 0) && (up == 0x3F));
103 uint8_t failc1 = ((up == 0) && (down == 0x3F));
104
105 /* print error message on failure */
106 if (failc0 || failc1) {
107 if (fails == 0) {
108 LOG_ERR("DDR error in fixing up");
109 }
110 char slicelsc = '0';
111 char slicemsc = '0';
112
113 fails |= (1 << dq);
114 slicelsc += (dq % 10);
115 slicemsc += (dq / 10);
116
117 LOG_ERR("S %c%c%c", slicemsc, slicelsc, failc0 ? 'U' : 'D');
118 }
119 }
120 }
121
ddr_phy_fixup(struct ddr_ctrl_data * ddr_ctrl)122 static inline uint64_t ddr_phy_fixup(struct ddr_ctrl_data *ddr_ctrl)
123 {
124 /* return bitmask of failed lanes */
125 uint32_t slicebase = 0;
126 uint32_t updownreg;
127
128 /* check errata condition */
129 for (uint32_t slice = 0; slice < 8; slice++) {
130 uint32_t regbase = slicebase + 34;
131
132 for (uint32_t reg = 0 ; reg < 4; reg++) {
133 updownreg = DDR_PHY_REG(ddr_ctrl, (regbase + reg));
134 check_errata(regbase, updownreg);
135 }
136 slicebase += 128;
137 }
138 return (0);
139 }
140
ddr_init(const struct device * dev)141 static int ddr_init(const struct device *dev)
142 {
143 struct ddr_ctrl_data *ddr_ctrl = dev->data;
144
145 LOG_DBG("start: 0x%lx", (uintptr_t)ddr_ctrl->ddr_start);
146 LOG_DBG("size: 0x%lx", ddr_ctrl->ddr_size);
147
148 ddr_writeregmap(ddr_ctrl);
149
150 DDR_CTL_REG(ddr_ctrl, 120) |= DISABLE_RD_INTERLEAVE;
151 DDR_CTL_REG(ddr_ctrl, 21) &= ~OPTIMAL_RMODW_EN;
152 DDR_CTL_REG(ddr_ctrl, 170) |= WRLVL_EN | DFI_PHY_WRLELV_MODE;
153 DDR_CTL_REG(ddr_ctrl, 181) |= DFI_PHY_RDLVL_MODE;
154 DDR_CTL_REG(ddr_ctrl, 260) |= RDLVL_EN;
155 DDR_CTL_REG(ddr_ctrl, 260) |= RDLVL_GATE_EN;
156 DDR_CTL_REG(ddr_ctrl, 182) |= DFI_PHY_RDLVL_GATE_MODE;
157
158 if (ddr_getdramclass(ddr_ctrl) == DRAM_CLASS_DDR4) {
159 DDR_CTL_REG(ddr_ctrl, 184) |= VREF_EN;
160 }
161
162 DDR_CTL_REG(ddr_ctrl, 136) |= LEVELING_OPERATION_COMPLETED;
163 DDR_CTL_REG(ddr_ctrl, 136) |= MC_INIT_COMPLETE;
164 DDR_CTL_REG(ddr_ctrl, 136) |= OUT_OF_RANGE | MULTIPLE_OUT_OF_RANGE;
165
166 /* Setup range protection */
167 size_t end_addr_16Kblocks = ((ddr_ctrl->ddr_size >> 14) & 0x7FFFFF) - 1;
168
169 DDR_CTL_REG(ddr_ctrl, 209) = 0x0;
170 DDR_CTL_REG(ddr_ctrl, 210) = ((uint32_t) end_addr_16Kblocks);
171 DDR_CTL_REG(ddr_ctrl, 212) = 0x0;
172 DDR_CTL_REG(ddr_ctrl, 214) = 0x0;
173 DDR_CTL_REG(ddr_ctrl, 216) = 0x0;
174 DDR_CTL_REG(ddr_ctrl, 224) |= AXI0_RANGE_PROT_BITS_0;
175 DDR_CTL_REG(ddr_ctrl, 225) = 0xFFFFFFFF;
176 DDR_CTL_REG(ddr_ctrl, 208) |= AXI0_ADDRESS_RANGE_ENABLE;
177 DDR_CTL_REG(ddr_ctrl, 208) |= PORT_ADDR_PROTECTION_EN;
178
179 /* Mask port command error interrupt */
180 DDR_CTL_REG(ddr_ctrl, 136) |= PORT_COMMAND_CHANNEL_ERROR;
181
182 DDR_CTL_REG(ddr_ctrl, 0) |= 1;
183 /* WAIT for initialization complete : bit 8 of INT_STATUS (DENALI_CTL_132) 0x210 */
184 while ((DDR_CTL_REG(ddr_ctrl, 132) & MC_INIT_COMPLETE) != 0) {
185 ;
186 }
187
188 uint64_t ddr_end = (uint64_t)ddr_ctrl->ddr_start + ddr_ctrl->ddr_size;
189
190 /* Disable the BusBlocker in front of the controller AXI slave ports */
191 volatile uint64_t *filterreg = (volatile uint64_t *)ddr_ctrl->ddr_physical_filter;
192
193 filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2);
194 /* ^^ RWX + TOR */
195
196 ddr_phy_fixup(ddr_ctrl);
197 return 0;
198 }
199
200 #define DDRCTL_NODE DT_NODELABEL(dmc)
201
202 static struct ddr_ctrl_data ddrctl_private_data = {
203 .ddrctl = (uint32_t *)DT_REG_ADDR_BY_IDX(DDRCTL_NODE, 0),
204 .ddrphy = (uint32_t *)DT_REG_ADDR_BY_IDX(DDRCTL_NODE, 1),
205 .ddr_physical_filter = (uint32_t *)DT_REG_ADDR_BY_IDX(DDRCTL_NODE, 2),
206
207 .ddr_start = (uint32_t *)DT_REG_ADDR(DT_NODELABEL(ram0)),
208 .ddr_size = DT_REG_SIZE(DT_NODELABEL(ram0)),
209 };
210
211 DEVICE_DT_INST_DEFINE(0, ddr_init, NULL, &ddrctl_private_data, NULL, POST_KERNEL,
212 CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, NULL);
213
