1 /*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_s32_gmac_mdio
8
9 #include <zephyr/logging/log.h>
10 LOG_MODULE_REGISTER(nxp_s32_mdio, CONFIG_MDIO_LOG_LEVEL);
11
12 #include <zephyr/kernel.h>
13 #include <zephyr/device.h>
14 #include <zephyr/drivers/mdio.h>
15 #include <zephyr/drivers/pinctrl.h>
16 #include <zephyr/drivers/clock_control.h>
17
18 #include <Gmac_Ip.h>
19
20 #define GMAC_MDIO_REG_OFFSET (0x200)
21
22 #define GMAC_STATUS_TO_ERRNO(x) \
23 ((x) == GMAC_STATUS_SUCCESS ? 0 : ((x) == GMAC_STATUS_TIMEOUT ? -ETIMEDOUT : -EIO))
24
25 struct mdio_nxp_s32_config {
26 uint8_t instance;
27 bool suppress_preamble;
28 const struct pinctrl_dev_config *pincfg;
29 const struct device *clock_dev;
30 clock_control_subsys_t clock_subsys;
31 };
32
33 struct mdio_nxp_s32_data {
34 struct k_mutex bus_mutex;
35 uint32_t clock_freq;
36 };
37
mdio_nxp_s32_read_c45(const struct device * dev,uint8_t prtad,uint8_t devad,uint16_t regad,uint16_t * regval)38 static int mdio_nxp_s32_read_c45(const struct device *dev, uint8_t prtad, uint8_t devad,
39 uint16_t regad, uint16_t *regval)
40 {
41 const struct mdio_nxp_s32_config *const cfg = dev->config;
42 struct mdio_nxp_s32_data *data = dev->data;
43 Gmac_Ip_StatusType status;
44
45 k_mutex_lock(&data->bus_mutex, K_FOREVER);
46
47 /* Configure MDIO controller before initiating a transmission */
48 Gmac_Ip_EnableMDIO(cfg->instance, cfg->suppress_preamble, data->clock_freq);
49
50 status = Gmac_Ip_MDIOReadMMD(cfg->instance, prtad, devad, regad, regval,
51 CONFIG_MDIO_NXP_S32_TIMEOUT);
52
53 k_mutex_unlock(&data->bus_mutex);
54
55 return GMAC_STATUS_TO_ERRNO(status);
56 }
57
mdio_nxp_s32_write_c45(const struct device * dev,uint8_t prtad,uint8_t devad,uint16_t regad,uint16_t regval)58 static int mdio_nxp_s32_write_c45(const struct device *dev, uint8_t prtad, uint8_t devad,
59 uint16_t regad, uint16_t regval)
60 {
61 const struct mdio_nxp_s32_config *const cfg = dev->config;
62 struct mdio_nxp_s32_data *data = dev->data;
63 Gmac_Ip_StatusType status;
64
65 k_mutex_lock(&data->bus_mutex, K_FOREVER);
66
67 /* Configure MDIO controller before initiating a transmission */
68 Gmac_Ip_EnableMDIO(cfg->instance, cfg->suppress_preamble, data->clock_freq);
69
70 status = Gmac_Ip_MDIOWriteMMD(cfg->instance, prtad, devad, regad, regval,
71 CONFIG_MDIO_NXP_S32_TIMEOUT);
72
73 k_mutex_unlock(&data->bus_mutex);
74
75 return GMAC_STATUS_TO_ERRNO(status);
76 }
77
mdio_nxp_s32_read_c22(const struct device * dev,uint8_t prtad,uint8_t regad,uint16_t * regval)78 static int mdio_nxp_s32_read_c22(const struct device *dev, uint8_t prtad,
79 uint8_t regad, uint16_t *regval)
80 {
81 const struct mdio_nxp_s32_config *const cfg = dev->config;
82 struct mdio_nxp_s32_data *data = dev->data;
83 Gmac_Ip_StatusType status;
84
85 k_mutex_lock(&data->bus_mutex, K_FOREVER);
86
87 /* Configure MDIO controller before initiating a transmission */
88 Gmac_Ip_EnableMDIO(cfg->instance, cfg->suppress_preamble, data->clock_freq);
89
90 status = Gmac_Ip_MDIORead(cfg->instance, prtad, regad, regval,
91 CONFIG_MDIO_NXP_S32_TIMEOUT);
92
93 k_mutex_unlock(&data->bus_mutex);
94
95 return GMAC_STATUS_TO_ERRNO(status);
96 }
97
mdio_nxp_s32_write_c22(const struct device * dev,uint8_t prtad,uint8_t regad,uint16_t regval)98 static int mdio_nxp_s32_write_c22(const struct device *dev, uint8_t prtad,
99 uint8_t regad, uint16_t regval)
100 {
101 const struct mdio_nxp_s32_config *const cfg = dev->config;
102 struct mdio_nxp_s32_data *data = dev->data;
103 Gmac_Ip_StatusType status;
104
105 k_mutex_lock(&data->bus_mutex, K_FOREVER);
106
107 /* Configure MDIO controller before initiating a transmission */
108 Gmac_Ip_EnableMDIO(cfg->instance, cfg->suppress_preamble, data->clock_freq);
109
110 status = Gmac_Ip_MDIOWrite(cfg->instance, prtad, regad, regval,
111 CONFIG_MDIO_NXP_S32_TIMEOUT);
112
113 k_mutex_unlock(&data->bus_mutex);
114
115 return GMAC_STATUS_TO_ERRNO(status);
116 }
117
mdio_nxp_s32_init(const struct device * dev)118 static int mdio_nxp_s32_init(const struct device *dev)
119 {
120 const struct mdio_nxp_s32_config *const cfg = dev->config;
121 struct mdio_nxp_s32_data *data = dev->data;
122 int err;
123
124 if (!device_is_ready(cfg->clock_dev)) {
125 LOG_ERR("Clock control device not ready");
126 return -ENODEV;
127 }
128
129 if (clock_control_get_rate(cfg->clock_dev, cfg->clock_subsys, &data->clock_freq)) {
130 LOG_ERR("Failed to get clock frequency");
131 return -EIO;
132 }
133
134 err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
135 if (err != 0) {
136 return err;
137 }
138
139 k_mutex_init(&data->bus_mutex);
140
141 return 0;
142 }
143
mdio_nxp_s32_noop(const struct device * dev)144 static void mdio_nxp_s32_noop(const struct device *dev)
145 {
146 ARG_UNUSED(dev);
147 /* Controller does not support enabling/disabling MDIO bus */
148 }
149
150 static const struct mdio_driver_api mdio_nxp_s32_driver_api = {
151 .read = mdio_nxp_s32_read_c22,
152 .write = mdio_nxp_s32_write_c22,
153 .read_c45 = mdio_nxp_s32_read_c45,
154 .write_c45 = mdio_nxp_s32_write_c45,
155 .bus_enable = mdio_nxp_s32_noop,
156 .bus_disable = mdio_nxp_s32_noop,
157 };
158
159 #define MDIO_NXP_S32_HW_INSTANCE_CHECK(i, n) \
160 (((DT_INST_REG_ADDR(n) - GMAC_MDIO_REG_OFFSET) == IP_GMAC_##i##_BASE) ? i : 0)
161
162 #define MDIO_NXP_S32_HW_INSTANCE(n) \
163 LISTIFY(__DEBRACKET FEATURE_GMAC_NUM_INSTANCES, \
164 MDIO_NXP_S32_HW_INSTANCE_CHECK, (|), n)
165
166 #define MDIO_NXP_S32_DEVICE(n) \
167 PINCTRL_DT_INST_DEFINE(n); \
168 static struct mdio_nxp_s32_data mdio_nxp_s32_data_##n; \
169 static const struct mdio_nxp_s32_config mdio_nxp_s32_config_##n = { \
170 .instance = MDIO_NXP_S32_HW_INSTANCE(n), \
171 .suppress_preamble = (bool)DT_INST_PROP(n, suppress_preamble), \
172 .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
173 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
174 .clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \
175 }; \
176 DEVICE_DT_INST_DEFINE(n, \
177 &mdio_nxp_s32_init, \
178 NULL, \
179 &mdio_nxp_s32_data_##n, \
180 &mdio_nxp_s32_config_##n, \
181 POST_KERNEL, \
182 CONFIG_MDIO_INIT_PRIORITY, \
183 &mdio_nxp_s32_driver_api);
184
185 DT_INST_FOREACH_STATUS_OKAY(MDIO_NXP_S32_DEVICE)
186
