1 /*
2 * Copyright (c) 2018 Foundries.io
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT openisa_rv32m1_intmux
8
9 /**
10 * @file
11 * @brief RV32M1 INTMUX (interrupt multiplexer) driver
12 *
13 * This driver provides support for level 2 interrupts on the RV32M1
14 * SoC using the INTMUX peripheral.
15 *
16 * Each of the RI5CY and ZERO-RISCY cores has an INTMUX peripheral;
17 * INTMUX0 is wired to the RI5CY event unit interrupt table, while
18 * INTMUX1 is used with ZERO-RISCY.
19 *
20 * For this reason, only a single intmux device is declared here. The
21 * dtsi for each core needs to set up the intmux device and any
22 * associated IRQ numbers to work with this driver.
23 */
24
25 #include <zephyr/kernel.h>
26 #include <zephyr/drivers/clock_control.h>
27 #include <zephyr/init.h>
28 #include <zephyr/irq.h>
29 #include <zephyr/irq_nextlevel.h>
30 #include <zephyr/sw_isr_table.h>
31 #include <soc.h>
32 #include <zephyr/dt-bindings/interrupt-controller/openisa-intmux.h>
33
34 /*
35 * CHn_VEC registers are offset by a value that is convenient if
36 * you're dealing with a Cortex-M NVIC vector table; we're not, so it
37 * needs to be subtracted out to get a useful value.
38 */
39 #define VECN_OFFSET 48U
40
41 struct rv32m1_intmux_config {
42 INTMUX_Type *regs;
43 const struct device *clock_dev;
44 clock_control_subsys_t clock_subsys;
45 struct _isr_table_entry *isr_base;
46 };
47
48 #define DEV_REGS(dev) (((const struct rv32m1_intmux_config *)(dev->config))->regs)
49
50 /*
51 * <irq_nextlevel.h> API
52 */
53
rv32m1_intmux_irq_enable(const struct device * dev,uint32_t irq)54 static void rv32m1_intmux_irq_enable(const struct device *dev, uint32_t irq)
55 {
56 INTMUX_Type *regs = DEV_REGS(dev);
57 uint32_t channel = rv32m1_intmux_channel(irq);
58 uint32_t line = rv32m1_intmux_line(irq);
59
60 regs->CHANNEL[channel].CHn_IER_31_0 |= BIT(line);
61 }
62
rv32m1_intmux_irq_disable(const struct device * dev,uint32_t irq)63 static void rv32m1_intmux_irq_disable(const struct device *dev, uint32_t irq)
64 {
65 INTMUX_Type *regs = DEV_REGS(dev);
66 uint32_t channel = rv32m1_intmux_channel(irq);
67 uint32_t line = rv32m1_intmux_line(irq);
68
69 regs->CHANNEL[channel].CHn_IER_31_0 &= ~BIT(line);
70 }
71
rv32m1_intmux_get_state(const struct device * dev)72 static uint32_t rv32m1_intmux_get_state(const struct device *dev)
73 {
74 INTMUX_Type *regs = DEV_REGS(dev);
75 size_t i;
76
77 for (i = 0; i < INTMUX_CHn_IER_31_0_COUNT; i++) {
78 if (regs->CHANNEL[i].CHn_IER_31_0) {
79 return 1;
80 }
81 }
82
83 return 0;
84 }
85
rv32m1_intmux_get_line_state(const struct device * dev,unsigned int irq)86 static int rv32m1_intmux_get_line_state(const struct device *dev,
87 unsigned int irq)
88 {
89 INTMUX_Type *regs = DEV_REGS(dev);
90 uint32_t channel = rv32m1_intmux_channel(irq);
91 uint32_t line = rv32m1_intmux_line(irq);
92
93 if ((regs->CHANNEL[channel].CHn_IER_31_0 & BIT(line)) != 0) {
94 return 1;
95 }
96
97 return 0;
98 }
99
100 /*
101 * IRQ handling.
102 */
103
104 #define ISR_ENTRY(channel, line) \
105 ((channel) * CONFIG_MAX_IRQ_PER_AGGREGATOR + line)
106
rv32m1_intmux_isr(const void * arg)107 static void rv32m1_intmux_isr(const void *arg)
108 {
109 const struct device *const dev = DEVICE_DT_INST_GET(0);
110 const struct rv32m1_intmux_config *config = dev->config;
111 INTMUX_Type *regs = DEV_REGS(dev);
112 uint32_t channel = POINTER_TO_UINT(arg);
113 uint32_t line = (regs->CHANNEL[channel].CHn_VEC >> 2);
114 struct _isr_table_entry *isr_base = config->isr_base;
115 struct _isr_table_entry *entry;
116
117 /*
118 * Make sure the vector is valid, there is a note of page 1243~1244
119 * of chapter 36 INTMUX of RV32M1 RM,
120 * Note: Unlike the NVIC, the INTMUX does not latch pending source
121 * interrupts. This means that the INTMUX output channel ISRs must
122 * check for and handle a 0 value of the CHn_VEC register to
123 * account for spurious interrupts.
124 */
125 if (line < VECN_OFFSET) {
126 return;
127 }
128
129 entry = &isr_base[ISR_ENTRY(channel, (line - VECN_OFFSET))];
130 entry->isr(entry->arg);
131 }
132
133 /*
134 * Instance and initialization
135 */
136
137 static const struct irq_next_level_api rv32m1_intmux_apis = {
138 .intr_enable = rv32m1_intmux_irq_enable,
139 .intr_disable = rv32m1_intmux_irq_disable,
140 .intr_get_state = rv32m1_intmux_get_state,
141 .intr_get_line_state = rv32m1_intmux_get_line_state,
142 };
143
144 static const struct rv32m1_intmux_config rv32m1_intmux_cfg = {
145 .regs = (INTMUX_Type *)DT_INST_REG_ADDR(0),
146 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
147 .clock_subsys = UINT_TO_POINTER(DT_INST_CLOCKS_CELL(0, name)),
148 .isr_base = &_sw_isr_table[CONFIG_2ND_LVL_ISR_TBL_OFFSET],
149 };
150
rv32m1_intmux_init(const struct device * dev)151 static int rv32m1_intmux_init(const struct device *dev)
152 {
153 const struct rv32m1_intmux_config *config = dev->config;
154 INTMUX_Type *regs = DEV_REGS(dev);
155 size_t i;
156
157 if (!device_is_ready(config->clock_dev)) {
158 return -ENODEV;
159 }
160
161 /* Enable INTMUX clock. */
162 clock_control_on(config->clock_dev, config->clock_subsys);
163
164 /*
165 * Reset all channels, not just the ones we're configured to
166 * support. We don't want to continue to take level 2 IRQs
167 * enabled by bootloaders, for example.
168 */
169 for (i = 0; i < INTMUX_CHn_CSR_COUNT; i++) {
170 regs->CHANNEL[i].CHn_CSR |= INTMUX_CHn_CSR_RST_MASK;
171 }
172
173 /* Connect and enable level 1 (channel) interrupts. */
174 #ifdef CONFIG_RV32M1_INTMUX_CHANNEL_0
175 IRQ_CONNECT(INTMUX_CH0_IRQ, 0, rv32m1_intmux_isr,
176 UINT_TO_POINTER(0), 0);
177 irq_enable(INTMUX_CH0_IRQ);
178 #endif
179 #ifdef CONFIG_RV32M1_INTMUX_CHANNEL_1
180 IRQ_CONNECT(INTMUX_CH1_IRQ, 0, rv32m1_intmux_isr,
181 UINT_TO_POINTER(1), 0);
182 irq_enable(INTMUX_CH1_IRQ);
183 #endif
184 #ifdef CONFIG_RV32M1_INTMUX_CHANNEL_2
185 IRQ_CONNECT(INTMUX_CH2_IRQ, 0, rv32m1_intmux_isr,
186 UINT_TO_POINTER(2), 0);
187 irq_enable(INTMUX_CH2_IRQ);
188 #endif
189 #ifdef CONFIG_RV32M1_INTMUX_CHANNEL_3
190 IRQ_CONNECT(INTMUX_CH3_IRQ, 0, rv32m1_intmux_isr,
191 UINT_TO_POINTER(3), 0);
192 irq_enable(INTMUX_CH3_IRQ);
193 #endif
194 #ifdef CONFIG_RV32M1_INTMUX_CHANNEL_4
195 IRQ_CONNECT(INTMUX_CH4_IRQ, 0, rv32m1_intmux_isr,
196 UINT_TO_POINTER(4), 0);
197 irq_enable(INTMUX_CH4_IRQ);
198 #endif
199 #ifdef CONFIG_RV32M1_INTMUX_CHANNEL_5
200 IRQ_CONNECT(INTMUX_CH5_IRQ, 0, rv32m1_intmux_isr,
201 UINT_TO_POINTER(5), 0);
202 irq_enable(INTMUX_CH5_IRQ);
203 #endif
204 #ifdef CONFIG_RV32M1_INTMUX_CHANNEL_6
205 IRQ_CONNECT(INTMUX_CH6_IRQ, 0, rv32m1_intmux_isr,
206 UINT_TO_POINTER(6), 0);
207 irq_enable(INTMUX_CH6_IRQ);
208 #endif
209 #ifdef CONFIG_RV32M1_INTMUX_CHANNEL_7
210 IRQ_CONNECT(INTMUX_CH7_IRQ, 0, rv32m1_intmux_isr,
211 UINT_TO_POINTER(7), 0);
212 irq_enable(INTMUX_CH7_IRQ);
213 #endif
214
215 return 0;
216 }
217
218 DEVICE_DT_INST_DEFINE(0, &rv32m1_intmux_init, NULL, NULL,
219 &rv32m1_intmux_cfg, PRE_KERNEL_1,
220 CONFIG_RV32M1_INTMUX_INIT_PRIORITY, &rv32m1_intmux_apis);
221
