1 /* 2 * Xilinx Processor System MIO / EMIO GPIO controller driver 3 * 4 * Driver private data declarations, GPIO bank module 5 * 6 * Copyright (c) 2022, Weidmueller Interface GmbH & Co. KG 7 * SPDX-License-Identifier: Apache-2.0 8 */ 9 10 #ifndef _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_BANK_H_ 11 #define _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_BANK_H_ 12 13 /* 14 * Register address calculation macros 15 * Register address offsets: comp. Zynq-7000 TRM, ug585, chap. B.19 16 */ 17 #define GPIO_XLNX_PS_BANK_MASK_DATA_LSW_REG (dev_conf->base_addr\ 18 + ((uint32_t)dev_conf->bank_index * 0x8)) 19 #define GPIO_XLNX_PS_BANK_MASK_DATA_MSW_REG ((dev_conf->base_addr + 0x04)\ 20 + ((uint32_t)dev_conf->bank_index * 0x8)) 21 #define GPIO_XLNX_PS_BANK_DATA_REG ((dev_conf->base_addr + 0x40)\ 22 + ((uint32_t)dev_conf->bank_index * 0x4)) 23 #define GPIO_XLNX_PS_BANK_DATA_RO_REG ((dev_conf->base_addr + 0x60)\ 24 + ((uint32_t)dev_conf->bank_index * 0x4)) 25 #define GPIO_XLNX_PS_BANK_DIRM_REG ((dev_conf->base_addr + 0x204)\ 26 + ((uint32_t)dev_conf->bank_index * 0x40)) 27 #define GPIO_XLNX_PS_BANK_OEN_REG ((dev_conf->base_addr + 0x208)\ 28 + ((uint32_t)dev_conf->bank_index * 0x40)) 29 #define GPIO_XLNX_PS_BANK_INT_MASK_REG ((dev_conf->base_addr + 0x20C)\ 30 + ((uint32_t)dev_conf->bank_index * 0x40)) 31 #define GPIO_XLNX_PS_BANK_INT_EN_REG ((dev_conf->base_addr + 0x210)\ 32 + ((uint32_t)dev_conf->bank_index * 0x40)) 33 #define GPIO_XLNX_PS_BANK_INT_DIS_REG ((dev_conf->base_addr + 0x214)\ 34 + ((uint32_t)dev_conf->bank_index * 0x40)) 35 #define GPIO_XLNX_PS_BANK_INT_STAT_REG ((dev_conf->base_addr + 0x218)\ 36 + ((uint32_t)dev_conf->bank_index * 0x40)) 37 #define GPIO_XLNX_PS_BANK_INT_TYPE_REG ((dev_conf->base_addr + 0x21C)\ 38 + ((uint32_t)dev_conf->bank_index * 0x40)) 39 #define GPIO_XLNX_PS_BANK_INT_POLARITY_REG ((dev_conf->base_addr + 0x220)\ 40 + ((uint32_t)dev_conf->bank_index * 0x40)) 41 #define GPIO_XLNX_PS_BANK_INT_ANY_REG ((dev_conf->base_addr + 0x224)\ 42 + ((uint32_t)dev_conf->bank_index * 0x40)) 43 44 /** 45 * @brief Run-time modifiable device data structure. 46 * 47 * This struct contains all data of a PS MIO / EMIO GPIO bank 48 * which is modifiable at run-time, such as the configuration 49 * parameters and current values of each individual pin belonging 50 * to the respective bank. 51 */ 52 struct gpio_xlnx_ps_bank_dev_data { 53 struct gpio_driver_data common; 54 sys_slist_t callbacks; 55 }; 56 57 /** 58 * @brief Constant device configuration data structure. 59 * 60 * This struct contains all data of a PS MIO / EMIO GPIO bank 61 * which is required for proper operation (such as base memory 62 * addresses etc.) which don't have to and therefore cannot be 63 * modified at run-time. 64 */ 65 struct gpio_xlnx_ps_bank_dev_cfg { 66 struct gpio_driver_config common; 67 68 uint32_t base_addr; 69 uint8_t bank_index; 70 }; 71 72 #endif /* _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_BANK_H_ */ 73
