1 /* 2 * Copyright (c) 2017 Erwin Rol <erwin@erwinrol.com> 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_STM32_HAL_PRIV_H_ 7 #define ZEPHYR_DRIVERS_ETHERNET_ETH_STM32_HAL_PRIV_H_ 8 9 #include <zephyr/kernel.h> 10 #include <zephyr/types.h> 11 12 #define ST_OUI_B0 0x00 13 #define ST_OUI_B1 0x80 14 #define ST_OUI_B2 0xE1 15 16 #define ETH_STM32_HAL_MTU NET_ETH_MTU 17 #define ETH_STM32_HAL_FRAME_SIZE_MAX (ETH_STM32_HAL_MTU + 18) 18 19 /* Definition of the Ethernet driver buffers size and count */ 20 #define ETH_STM32_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ 21 #define ETH_STM32_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ 22 23 /* Device constant configuration parameters */ 24 struct eth_stm32_hal_dev_cfg { 25 void (*config_func)(void); 26 struct stm32_pclken pclken; 27 struct stm32_pclken pclken_rx; 28 struct stm32_pclken pclken_tx; 29 #if DT_INST_CLOCKS_HAS_NAME(0, mac_clk_ptp) 30 struct stm32_pclken pclken_ptp; 31 #endif 32 const struct pinctrl_dev_config *pcfg; 33 }; 34 35 /* Device run time data */ 36 struct eth_stm32_hal_dev_data { 37 struct net_if *iface; 38 uint8_t mac_addr[6]; 39 ETH_HandleTypeDef heth; 40 /* clock device */ 41 const struct device *clock; 42 struct k_mutex tx_mutex; 43 struct k_sem rx_int_sem; 44 #if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X) || \ 45 defined(CONFIG_ETH_STM32_HAL_API_V2) 46 struct k_sem tx_int_sem; 47 #endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X || CONFIG_ETH_STM32_HAL_API_V2*/ 48 K_KERNEL_STACK_MEMBER(rx_thread_stack, 49 CONFIG_ETH_STM32_HAL_RX_THREAD_STACK_SIZE); 50 struct k_thread rx_thread; 51 bool link_up; 52 #if defined(CONFIG_PTP_CLOCK_STM32_HAL) 53 const struct device *ptp_clock; 54 float clk_ratio; 55 float clk_ratio_adj; 56 #endif /* CONFIG_PTP_CLOCK_STM32_HAL */ 57 #if defined(CONFIG_NET_STATISTICS_ETHERNET) 58 struct net_stats_eth stats; 59 #endif 60 }; 61 62 #endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_STM32_HAL_PRIV_H_ */ 63
