1 /*
2 * Copyright (c) 2019 Intel Corporation
3 * Copyright (c) 2022 Microchip Technology Inc.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT microchip_xec_espi_saf_v2
9
10 #include <zephyr/kernel.h>
11 #include <soc.h>
12 #include <errno.h>
13 #include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
14 #include <zephyr/drivers/espi.h>
15 #include <zephyr/drivers/espi_saf.h>
16 #include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
17 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
18 #include <zephyr/logging/log.h>
19
20 #include "espi_mchp_xec_v2.h"
21 #include "espi_utils.h"
22 LOG_MODULE_REGISTER(espi_saf, CONFIG_ESPI_LOG_LEVEL);
23
24 /* common clock control device node for all Microchip XEC chips */
25 #define MCHP_XEC_CLOCK_CONTROL_NODE DT_NODELABEL(pcr)
26
27 /* SAF EC Portal read/write flash access limited to 1-64 bytes */
28 #define MAX_SAF_ECP_BUFFER_SIZE 64ul
29
30 /* 1 second maximum for flash operations */
31 #define MAX_SAF_FLASH_TIMEOUT 125000ul /* 1000ul */
32
33 #define MAX_SAF_FLASH_TIMEOUT_MS 1000ul
34
35 /* 64 bytes @ 24MHz quad is approx. 6 us */
36 #define SAF_WAIT_INTERVAL 8
37
38 /* After 8 wait intervals yield */
39 #define SAF_YIELD_THRESHOLD 64
40
41 /* Get QMSPI 0 encoded GIRQ information */
42 #define XEC_QMSPI_ENC_GIRQ \
43 DT_PROP_BY_IDX(DT_INST(0, microchip_xec_qmspi_ldma), girqs, 0)
44
45 #define XEC_QMSPI_GIRQ MCHP_XEC_ECIA_GIRQ(XEC_QMSPI_ENC_GIRQ)
46 #define XEC_QMSPI_GIRQ_POS MCHP_XEC_ECIA_GIRQ_POS(XEC_QMSPI_ENC_GIRQ)
47
48 #define XEC_SAF_DONE_ENC_GIRQ DT_INST_PROP_BY_IDX(0, girqs, 0)
49 #define XEC_SAF_ERR_ENC_GIRQ DT_INST_PROP_BY_IDX(0, girqs, 1)
50
51 #define XEC_SAF_DONE_GIRQ MCHP_XEC_ECIA_GIRQ(XEC_SAF_DONE_ENC_GIRQ)
52 #define XEC_SAF_DONE_GIRQ_POS MCHP_XEC_ECIA_GIRQ_POS(XEC_SAF_ERR_ENC_GIRQ)
53
54 /*
55 * SAF configuration from Device Tree
56 * SAF controller register block base address
57 * QMSPI controller register block base address
58 * SAF communications register block base address
59 * Flash STATUS1 poll timeout in 32KHz periods
60 * Flash consecutive read timeout in units of 20 ns
61 * Delay before first Poll-1 command after suspend in 20 ns units
62 * Hold off suspend for this interval if erase or program in 32KHz periods.
63 * Add delay between Poll STATUS1 commands in 20 ns units.
64 */
65 struct espi_saf_xec_config {
66 struct mchp_espi_saf * const saf_base;
67 struct qmspi_regs * const qmspi_base;
68 struct mchp_espi_saf_comm * const saf_comm_base;
69 struct espi_iom_regs * const iom_base;
70 void (*irq_config_func)(void);
71 uint32_t poll_timeout;
72 uint32_t consec_rd_timeout;
73 uint32_t sus_chk_delay;
74 uint16_t sus_rsm_interval;
75 uint16_t poll_interval;
76 uint8_t pcr_idx;
77 uint8_t pcr_pos;
78 uint8_t irq_info_size;
79 uint8_t rsvd1;
80 const struct espi_xec_irq_info *irq_info_list;
81 };
82
83 struct espi_saf_xec_data {
84 struct k_sem ecp_lock;
85 uint32_t hwstatus;
86 sys_slist_t callbacks;
87 };
88
89 /* EC portal local flash r/w buffer */
90 static uint32_t slave_mem[MAX_SAF_ECP_BUFFER_SIZE];
91
92 /*
93 * @brief eSPI SAF configuration
94 */
95
mchp_saf_cs_descr_wr(struct mchp_espi_saf * regs,uint8_t cs,uint32_t val)96 static inline void mchp_saf_cs_descr_wr(struct mchp_espi_saf *regs, uint8_t cs,
97 uint32_t val)
98 {
99 regs->SAF_CS_OP[cs].OP_DESCR = val;
100 }
101
mchp_saf_poll2_mask_wr(struct mchp_espi_saf * regs,uint8_t cs,uint16_t val)102 static inline void mchp_saf_poll2_mask_wr(struct mchp_espi_saf *regs, uint8_t cs,
103 uint16_t val)
104 {
105 LOG_DBG("%s cs: %d mask %x", __func__, cs, val);
106 if (cs == 0) {
107 regs->SAF_CS0_CFG_P2M = val;
108 } else {
109 regs->SAF_CS1_CFG_P2M = val;
110 }
111 }
112
mchp_saf_cm_prefix_wr(struct mchp_espi_saf * regs,uint8_t cs,uint16_t val)113 static inline void mchp_saf_cm_prefix_wr(struct mchp_espi_saf *regs, uint8_t cs,
114 uint16_t val)
115 {
116 if (cs == 0) {
117 regs->SAF_CS0_CM_PRF = val;
118 } else {
119 regs->SAF_CS1_CM_PRF = val;
120 }
121 }
122
123 /*
124 * Initialize SAF flash protection regions.
125 * SAF HW implements 17 protection regions.
126 * At least one protection region must be configured to allow
127 * EC access to the local flash through the EC Portal.
128 * Each protection region is composed of 4 32-bit registers
129 * Start bits[19:0] = bits[31:12] region start address (4KB boundaries)
130 * Limit bits[19:0] = bits[31:12] region limit address (4KB boundaries)
131 * Write protect b[7:0] = masters[7:0] allow write/erase. 1=allowed
132 * Read protetc b[7:0] = masters[7:0] allow read. 1=allowed
133 *
134 * This routine configures protection region 0 for full flash array
135 * address range and read-write-erase for all masters.
136 * This routine must be called AFTER the flash configuration size/limit and
137 * threshold registers have been programmed.
138 *
139 * POR default values:
140 * Start = 0x7ffff
141 * Limit = 0
142 * Write Prot = 0x01 Master 0 always granted write/erase
143 * Read Prot = 0x01 Master 0 always granted read
144 *
145 * Sample code configures PR[0]
146 * Start = 0
147 * Limit = 0x7ffff
148 * WR = 0xFF
149 * RD = 0xFF
150 */
saf_protection_regions_init(struct mchp_espi_saf * regs)151 static void saf_protection_regions_init(struct mchp_espi_saf *regs)
152 {
153 LOG_DBG("%s", __func__);
154
155 for (size_t n = 0; n < MCHP_ESPI_SAF_PR_MAX; n++) {
156 if (n == 0) {
157 regs->SAF_PROT_RG[0].START = 0U;
158 regs->SAF_PROT_RG[0].LIMIT =
159 regs->SAF_FL_CFG_SIZE_LIM >> 12;
160 regs->SAF_PROT_RG[0].WEBM = MCHP_SAF_MSTR_ALL;
161 regs->SAF_PROT_RG[0].RDBM = MCHP_SAF_MSTR_ALL;
162 } else {
163 regs->SAF_PROT_RG[n].START =
164 MCHP_SAF_PROT_RG_START_DFLT;
165 regs->SAF_PROT_RG[n].LIMIT =
166 MCHP_SAF_PROT_RG_LIMIT_DFLT;
167 regs->SAF_PROT_RG[n].WEBM = 0U;
168 regs->SAF_PROT_RG[n].RDBM = 0U;
169 }
170
171 LOG_DBG("PROT[%d] START %x", n, regs->SAF_PROT_RG[n].START);
172 LOG_DBG("PROT[%d] LIMIT %x", n, regs->SAF_PROT_RG[n].LIMIT);
173 LOG_DBG("PROT[%d] WEBM %x", n, regs->SAF_PROT_RG[n].WEBM);
174 LOG_DBG("PROT[%d] RDBM %x", n, regs->SAF_PROT_RG[n].RDBM);
175 }
176 }
177
qmspi_freq_div(uint32_t freqhz,uint32_t * fdiv)178 static int qmspi_freq_div(uint32_t freqhz, uint32_t *fdiv)
179 {
180 clock_control_subsys_t clkss =
181 (clock_control_subsys_t)(MCHP_XEC_PCR_CLK_PERIPH_FAST);
182 uint32_t clk = 0u;
183
184 if (!fdiv) {
185 return -EINVAL;
186 }
187
188 if (clock_control_get_rate(DEVICE_DT_GET(MCHP_XEC_CLOCK_CONTROL_NODE),
189 (clock_control_subsys_t)clkss, &clk)) {
190 return -EIO;
191 }
192
193 *fdiv = 0u; /* maximum divider = 0x10000 */
194 if (freqhz) {
195 *fdiv = clk / freqhz;
196 }
197
198 return 0u;
199 }
200
qmspi_freq_div_from_mhz(uint32_t freqmhz,uint32_t * fdiv)201 static int qmspi_freq_div_from_mhz(uint32_t freqmhz, uint32_t *fdiv)
202 {
203 uint32_t freqhz = freqmhz * 1000000u;
204
205 return qmspi_freq_div(freqhz, fdiv);
206 }
207
208 /*
209 * Take over and re-initialize QMSPI for use by SAF HW engine.
210 * When SAF is activated, QMSPI registers are controlled by SAF
211 * HW engine. CPU no longer has access to QMSPI registers.
212 * 1. Save QMSPI driver frequency divider, SPI signalling mode, and
213 * chip select timing.
214 * 2. Put QMSPI controller in a known state by performing a soft reset.
215 * 3. Clear QMSPI GIRQ status
216 * 4. Configure QMSPI interface control for SAF.
217 * 5. Load flash device independent (generic) descriptors.
218 * 6. Enable transfer done interrupt in QMSPI
219 * 7. Enable QMSPI SAF mode
220 * 8. If user configuration overrides frequency, signalling mode,
221 * or chip select timing derive user values.
222 * 9. Program QMSPI MODE and CSTIM registers with activate set.
223 */
saf_qmspi_init(const struct espi_saf_xec_config * xcfg,const struct espi_saf_cfg * cfg)224 static int saf_qmspi_init(const struct espi_saf_xec_config *xcfg,
225 const struct espi_saf_cfg *cfg)
226 {
227 uint32_t qmode, qfdiv, cstim, n;
228 struct qmspi_regs * const qregs = xcfg->qmspi_base;
229 struct mchp_espi_saf * const regs = xcfg->saf_base;
230 const struct espi_saf_hw_cfg *hwcfg = &cfg->hwcfg;
231
232 qmode = qregs->MODE;
233 if (!(qmode & MCHP_QMSPI_M_ACTIVATE)) {
234 return -EAGAIN;
235 }
236
237 qmode = qregs->MODE & (MCHP_QMSPI_M_FDIV_MASK | MCHP_QMSPI_M_SIG_MASK);
238 cstim = qregs->CSTM;
239 qregs->MODE = MCHP_QMSPI_M_SRST;
240 qregs->STS = MCHP_QMSPI_STS_RW1C_MASK;
241
242 mchp_soc_ecia_girq_src_dis(XEC_QMSPI_GIRQ, XEC_QMSPI_GIRQ_POS);
243 mchp_soc_ecia_girq_src_clr(XEC_QMSPI_GIRQ, XEC_QMSPI_GIRQ_POS);
244
245 qregs->IFCTRL =
246 (MCHP_QMSPI_IFC_WP_OUT_HI | MCHP_QMSPI_IFC_WP_OUT_EN |
247 MCHP_QMSPI_IFC_HOLD_OUT_HI | MCHP_QMSPI_IFC_HOLD_OUT_EN);
248
249 for (n = 0; n < MCHP_SAF_NUM_GENERIC_DESCR; n++) {
250 qregs->DESCR[MCHP_SAF_CM_EXIT_START_DESCR + n] =
251 hwcfg->generic_descr[n];
252 }
253
254 /* SAF HW uses QMSPI interrupt signal */
255 qregs->IEN = MCHP_QMSPI_IEN_XFR_DONE;
256
257 qmode |= (MCHP_QMSPI_M_SAF_DMA_MODE_EN | MCHP_QMSPI_M_CS0 |
258 MCHP_QMSPI_M_ACTIVATE);
259
260 if (hwcfg->flags & MCHP_SAF_HW_CFG_FLAG_CPHA) {
261 qmode = (qmode & ~(MCHP_QMSPI_M_SIG_MASK)) |
262 ((hwcfg->qmspi_cpha << MCHP_QMSPI_M_SIG_POS) &
263 MCHP_QMSPI_M_SIG_MASK);
264 }
265
266
267 /* Copy QMSPI frequency divider into SAF CS0 and CS1 QMSPI frequency
268 * dividers. SAF HW uses CS0/CS1 divider register fields to overwrite
269 * QMSPI frequency divider in QMSPI.Mode register. Later we will update
270 * SAF CS0/CS1 SPI frequency dividers based on flash configuration.
271 */
272 qfdiv = (qmode & MCHP_QMSPI_M_FDIV_MASK) >> MCHP_QMSPI_M_FDIV_POS;
273 qfdiv = qfdiv | (qfdiv << 16); /* read and rest clock dividers */
274 regs->SAF_CLKDIV_CS0 = qfdiv;
275 regs->SAF_CLKDIV_CS1 = qfdiv;
276
277 if (hwcfg->flags & MCHP_SAF_HW_CFG_FLAG_CSTM) {
278 cstim = hwcfg->qmspi_cs_timing;
279 }
280
281 /* MEC172x SAF uses TX LDMA channel 0 in non-descriptor mode.
282 * SAF HW writes QMSPI.Control and TX LDMA channel 0 registers
283 * to transmit opcode, address, and data. We configure must
284 * configure TX LDMA channel 0 control register. We believe SAF
285 * HW will set bit[6] to 1.
286 */
287 qregs->LDTX[0].CTRL = MCHP_QMSPI_LDC_EN | MCHP_QMSPI_LDC_RS_EN | MCHP_QMSPI_LDC_ASZ_4;
288
289 qmode |= MCHP_QMSPI_M_LDMA_RX_EN | MCHP_QMSPI_M_LDMA_TX_EN;
290
291 qregs->MODE = qmode;
292 qregs->CSTM = cstim;
293
294 return 0;
295 }
296
297 /*
298 * Registers at offsets:
299 * SAF Poll timeout @ 0x194. Hard coded to 0x28000. Default value = 0.
300 * recommended value = 0x28000 32KHz clocks (5 seconds). b[17:0]
301 * SAF Poll interval @ 0x198. Hard coded to 0
302 * Default value = 0. Recommended = 0. b[15:0]
303 * SAF Suspend/Resume Interval @ 0x19c. Hard coded to 0x8
304 * Default value = 0x01. Min time erase/prog in 32KHz units.
305 * SAF Consecutive Read Timeout @ 0x1a0. Hard coded to 0x2. b[15:0]
306 * Units of MCLK. Recommend < 20us. b[19:0]
307 * SAF Suspend Check Delay @ 0x1ac. Not touched.
308 * Default = 0. Recommend = 20us. Units = MCLK. b[19:0]
309 */
saf_flash_timing_init(struct mchp_espi_saf * const regs,const struct espi_saf_xec_config * cfg)310 static void saf_flash_timing_init(struct mchp_espi_saf * const regs,
311 const struct espi_saf_xec_config *cfg)
312 {
313 LOG_DBG("%s\n", __func__);
314 regs->SAF_POLL_TMOUT = cfg->poll_timeout;
315 regs->SAF_POLL_INTRVL = cfg->poll_interval;
316 regs->SAF_SUS_RSM_INTRVL = cfg->sus_rsm_interval;
317 regs->SAF_CONSEC_RD_TMOUT = cfg->consec_rd_timeout;
318 regs->SAF_SUS_CHK_DLY = cfg->sus_chk_delay;
319 LOG_DBG("SAF_POLL_TMOUT %x\n", regs->SAF_POLL_TMOUT);
320 LOG_DBG("SAF_POLL_INTRVL %x\n", regs->SAF_POLL_INTRVL);
321 LOG_DBG("SAF_SUS_RSM_INTRVL %x\n", regs->SAF_SUS_RSM_INTRVL);
322 LOG_DBG("SAF_CONSEC_RD_TMOUT %x\n", regs->SAF_CONSEC_RD_TMOUT);
323 LOG_DBG("SAF_SUS_CHK_DLY %x\n", regs->SAF_SUS_CHK_DLY);
324 }
325
326 /*
327 * Disable DnX bypass feature.
328 */
saf_dnx_bypass_init(struct mchp_espi_saf * const regs)329 static void saf_dnx_bypass_init(struct mchp_espi_saf * const regs)
330 {
331 regs->SAF_DNX_PROT_BYP = 0;
332 regs->SAF_DNX_PROT_BYP = 0xffffffff;
333 }
334
335 /*
336 * Bitmap of flash erase size from 1KB up to 128KB.
337 * eSPI SAF specification requires 4KB erase support.
338 * MCHP SAF supports 4KB, 32KB, and 64KB.
339 * Only report 32KB and 64KB to Host if supported by both
340 * flash devices.
341 */
saf_init_erase_block_size(const struct device * dev,const struct espi_saf_cfg * cfg)342 static int saf_init_erase_block_size(const struct device *dev, const struct espi_saf_cfg *cfg)
343 {
344 const struct espi_saf_xec_config * const xcfg = dev->config;
345 struct espi_iom_regs * const espi_iom = xcfg->iom_base;
346 struct espi_saf_flash_cfg *fcfg = cfg->flash_cfgs;
347 uint32_t opb = fcfg->opb;
348 uint8_t erase_bitmap = MCHP_ESPI_SERASE_SZ_4K;
349
350 LOG_DBG("%s\n", __func__);
351
352 if (cfg->nflash_devices > 1) {
353 fcfg++;
354 opb &= fcfg->opb;
355 }
356
357 if ((opb & MCHP_SAF_CS_OPB_ER0_MASK) == 0) {
358 /* One or both do not support 4KB erase! */
359 return -EINVAL;
360 }
361
362 if (opb & MCHP_SAF_CS_OPB_ER1_MASK) {
363 erase_bitmap |= MCHP_ESPI_SERASE_SZ_32K;
364 }
365
366 if (opb & MCHP_SAF_CS_OPB_ER2_MASK) {
367 erase_bitmap |= MCHP_ESPI_SERASE_SZ_64K;
368 }
369
370 espi_iom->SAFEBS = erase_bitmap;
371
372 return 0;
373 }
374
375 /*
376 * Set the continuous mode prefix and 4-byte address mode bits
377 * based upon the flash configuration information.
378 * Updates:
379 * SAF Flash Config Poll2 Mask @ 0x1A4
380 * SAF Flash Config Special Mode @ 0x1B0
381 * SAF Flash Misc Config @ 0x38
382 */
saf_flash_misc_cfg(struct mchp_espi_saf * const regs,uint8_t cs,const struct espi_saf_flash_cfg * fcfg)383 static void saf_flash_misc_cfg(struct mchp_espi_saf * const regs, uint8_t cs,
384 const struct espi_saf_flash_cfg *fcfg)
385 {
386 uint32_t d, v;
387
388 d = regs->SAF_FL_CFG_MISC;
389
390 v = MCHP_SAF_FL_CFG_MISC_CS0_CPE;
391 if (cs) {
392 v = MCHP_SAF_FL_CFG_MISC_CS1_CPE;
393 }
394
395 /* Does this flash device require a prefix for continuous mode? */
396 if (fcfg->cont_prefix != 0) {
397 d |= v;
398 } else {
399 d &= ~v;
400 }
401
402 v = MCHP_SAF_FL_CFG_MISC_CS0_4BM;
403 if (cs) {
404 v = MCHP_SAF_FL_CFG_MISC_CS1_4BM;
405 }
406
407 /* Use 32-bit addressing for this flash device? */
408 if (fcfg->flags & MCHP_FLASH_FLAG_ADDR32) {
409 d |= v;
410 } else {
411 d &= ~v;
412 }
413
414 regs->SAF_FL_CFG_MISC = d;
415 LOG_DBG("%s SAF_FL_CFG_MISC: %x", __func__, d);
416 }
417
saf_flash_pd_cfg(struct mchp_espi_saf * const regs,uint8_t cs,const struct espi_saf_flash_cfg * fcfg)418 static void saf_flash_pd_cfg(struct mchp_espi_saf * const regs, uint8_t cs,
419 const struct espi_saf_flash_cfg *fcfg)
420 {
421 uint32_t pdval = 0u;
422 uint32_t msk = 0u;
423
424 if (cs == 0) {
425 msk = BIT(SAF_PWRDN_CTRL_CS0_PD_EN_POS) | BIT(SAF_PWRDN_CTRL_CS0_PD_EN_POS);
426 if (fcfg->flags & MCHP_FLASH_FLAG_V2_PD_CS0_EN) {
427 pdval |= BIT(SAF_PWRDN_CTRL_CS0_PD_EN_POS);
428 }
429 if (fcfg->flags & MCHP_FLASH_FLAG_V2_PD_CS0_EC_WK_EN) {
430 pdval |= BIT(SAF_PWRDN_CTRL_CS0_WPA_EN_POS);
431 }
432 } else {
433 msk = BIT(SAF_PWRDN_CTRL_CS1_PD_EN_POS) | BIT(SAF_PWRDN_CTRL_CS1_PD_EN_POS);
434 if (fcfg->flags & MCHP_FLASH_FLAG_V2_PD_CS1_EN) {
435 pdval |= BIT(SAF_PWRDN_CTRL_CS1_PD_EN_POS);
436 }
437 if (fcfg->flags & MCHP_FLASH_FLAG_V2_PD_CS1_EC_WK_EN) {
438 pdval |= BIT(SAF_PWRDN_CTRL_CS1_PD_EN_POS);
439 }
440 }
441
442 regs->SAF_PWRDN_CTRL = (regs->SAF_PWRDN_CTRL & ~msk) | pdval;
443 }
444
445 /* Configure SAF per chip select QMSPI clock dividers.
446 * SAF HW implements two QMSP clock divider registers per chip select:
447 * Each divider register is composed of two 16-bit fields:
448 * b[15:0] = QMSPI clock divider for SPI read
449 * b[31:16] = QMSPI clock divider for all other SPI commands
450 */
saf_flash_freq_cfg(struct mchp_espi_saf * const regs,uint8_t cs,const struct espi_saf_flash_cfg * fcfg)451 static int saf_flash_freq_cfg(struct mchp_espi_saf * const regs, uint8_t cs,
452 const struct espi_saf_flash_cfg *fcfg)
453 {
454 uint32_t fmhz, fdiv, saf_qclk;
455
456 if (cs == 0) {
457 saf_qclk = regs->SAF_CLKDIV_CS0;
458 } else {
459 saf_qclk = regs->SAF_CLKDIV_CS1;
460 }
461
462 fmhz = fcfg->rd_freq_mhz;
463 if (fmhz) {
464 fdiv = 0u;
465 if (qmspi_freq_div_from_mhz(fmhz, &fdiv)) {
466 LOG_ERR("%s SAF CLKDIV CS0 bad freq MHz %u",
467 __func__, fmhz);
468 return -EIO;
469 }
470 if (fdiv) {
471 saf_qclk = (saf_qclk & ~SAF_CLKDIV_CS_MSK0) |
472 (fdiv & SAF_CLKDIV_CS_MSK0);
473 }
474 }
475
476 fmhz = fcfg->freq_mhz;
477 if (fmhz) {
478 fdiv = 0u;
479 if (qmspi_freq_div_from_mhz(fmhz, &fdiv)) {
480 LOG_ERR("%s SAF CLKDIV CS1 bad freq MHz %u",
481 __func__, fmhz);
482 return -EIO;
483 }
484 if (fdiv) {
485 saf_qclk &= ~(SAF_CLKDIV_CS_MSK0 << 16);
486 saf_qclk |= (fdiv & SAF_CLKDIV_CS_MSK0) << 16;
487 }
488 }
489
490 if (cs == 0) {
491 regs->SAF_CLKDIV_CS0 = saf_qclk;
492 } else {
493 regs->SAF_CLKDIV_CS1 = saf_qclk;
494 }
495
496 return 0;
497 }
498
499 /*
500 * Program flash device specific SAF and QMSPI registers.
501 *
502 * CS0 OpA @ 0x4c or CS1 OpA @ 0x5C
503 * CS0 OpB @ 0x50 or CS1 OpB @ 0x60
504 * CS0 OpC @ 0x54 or CS1 OpC @ 0x64
505 * Poll 2 Mask @ 0x1a4
506 * Continuous Prefix @ 0x1b0
507 * CS0: QMSPI descriptors 0-5 or CS1 QMSPI descriptors 6-11
508 * CS0 Descrs @ 0x58 or CS1 Descrs @ 0x68
509 * SAF CS0 QMSPI frequency dividers (read/all other) commands
510 * SAF CS1 QMSPI frequency dividers (read/all other) commands
511 */
saf_flash_cfg(const struct device * dev,const struct espi_saf_flash_cfg * fcfg,uint8_t cs)512 static int saf_flash_cfg(const struct device *dev,
513 const struct espi_saf_flash_cfg *fcfg, uint8_t cs)
514 {
515 uint32_t d, did;
516 const struct espi_saf_xec_config * const xcfg = dev->config;
517 struct mchp_espi_saf * const regs = xcfg->saf_base;
518 struct qmspi_regs * const qregs = xcfg->qmspi_base;
519
520 LOG_DBG("%s cs=%u", __func__, cs);
521
522 regs->SAF_CS_OP[cs].OPA = fcfg->opa;
523 regs->SAF_CS_OP[cs].OPB = fcfg->opb;
524 regs->SAF_CS_OP[cs].OPC = fcfg->opc;
525 regs->SAF_CS_OP[cs].OP_DESCR = (uint32_t)fcfg->cs_cfg_descr_ids;
526
527 did = MCHP_SAF_QMSPI_CS0_START_DESCR;
528 if (cs != 0) {
529 did = MCHP_SAF_QMSPI_CS1_START_DESCR;
530 }
531
532 for (size_t i = 0; i < MCHP_SAF_QMSPI_NUM_FLASH_DESCR; i++) {
533 d = fcfg->descr[i] & ~(MCHP_QMSPI_C_NEXT_DESCR_MASK);
534 d |= (((did + 1) << MCHP_QMSPI_C_NEXT_DESCR_POS) &
535 MCHP_QMSPI_C_NEXT_DESCR_MASK);
536 qregs->DESCR[did++] = d;
537 }
538
539 mchp_saf_poll2_mask_wr(regs, cs, fcfg->poll2_mask);
540 mchp_saf_cm_prefix_wr(regs, cs, fcfg->cont_prefix);
541 saf_flash_misc_cfg(regs, cs, fcfg);
542 saf_flash_pd_cfg(regs, cs, fcfg);
543
544 return saf_flash_freq_cfg(regs, cs, fcfg);
545 }
546
547 static const uint32_t tag_map_dflt[MCHP_ESPI_SAF_TAGMAP_MAX] = {
548 MCHP_SAF_TAG_MAP0_DFLT, MCHP_SAF_TAG_MAP1_DFLT, MCHP_SAF_TAG_MAP2_DFLT
549 };
550
saf_tagmap_init(struct mchp_espi_saf * const regs,const struct espi_saf_cfg * cfg)551 static void saf_tagmap_init(struct mchp_espi_saf * const regs,
552 const struct espi_saf_cfg *cfg)
553 {
554 const struct espi_saf_hw_cfg *hwcfg = &cfg->hwcfg;
555
556 for (int i = 0; i < MCHP_ESPI_SAF_TAGMAP_MAX; i++) {
557 if (hwcfg->tag_map[i] & MCHP_SAF_HW_CFG_TAGMAP_USE) {
558 regs->SAF_TAG_MAP[i] = hwcfg->tag_map[i];
559 } else {
560 regs->SAF_TAG_MAP[i] = tag_map_dflt[i];
561 }
562 }
563
564 LOG_DBG("SAF TAG0 %x", regs->SAF_TAG_MAP[0]);
565 LOG_DBG("SAF TAG1 %x", regs->SAF_TAG_MAP[1]);
566 LOG_DBG("SAF TAG2 %x", regs->SAF_TAG_MAP[2]);
567 }
568
569 #define SAF_QSPI_LDMA_CTRL \
570 (MCHP_QMSPI_LDC_EN | MCHP_QMSPI_LDC_RS_EN | \
571 MCHP_QMSPI_LDC_ASZ_4)
572
saf_qmspi_ldma_cfg(const struct espi_saf_xec_config * const xcfg)573 static void saf_qmspi_ldma_cfg(const struct espi_saf_xec_config * const xcfg)
574 {
575 struct qmspi_regs * const qregs = xcfg->qmspi_base;
576 uint32_t qmode = qregs->MODE;
577 uint32_t n, temp, chan;
578
579 qregs->MODE = qmode & ~(MCHP_QMSPI_M_ACTIVATE);
580
581 for (n = 0u; n < MCHP_QMSPI_MAX_DESCR; n++) {
582 temp = qregs->DESCR[n];
583 if (temp & MCHP_QMSPI_C_TX_MASK) {
584 chan = (temp & MCHP_QMSPI_C_TX_DMA_MASK) >> MCHP_QMSPI_C_TX_DMA_POS;
585 if (chan) { /* zero is disabled */
586 chan--; /* register array index starts at 0 */
587 qregs->LDMA_TX_DESCR_BM |= BIT(n);
588 qregs->LDTX[chan].CTRL = SAF_QSPI_LDMA_CTRL;
589 }
590 }
591 if (temp & MCHP_QMSPI_C_RX_EN) {
592 chan = (temp & MCHP_QMSPI_C_RX_DMA_MASK) >> MCHP_QMSPI_C_RX_DMA_POS;
593 if (chan) {
594 chan--;
595 qregs->LDMA_RX_DESCR_BM |= BIT(n);
596 qregs->LDRX[chan].CTRL = SAF_QSPI_LDMA_CTRL;
597 }
598 }
599 }
600
601 qregs->MODE = qmode;
602 }
603
604 /*
605 * Configure SAF and QMSPI for SAF operation based upon the
606 * number and characteristics of local SPI flash devices.
607 * NOTE: SAF is configured but not activated. SAF should be
608 * activated only when eSPI master sends Flash Channel enable
609 * message with MAF/SAF select flag.
610 */
espi_saf_xec_configuration(const struct device * dev,const struct espi_saf_cfg * cfg)611 static int espi_saf_xec_configuration(const struct device *dev,
612 const struct espi_saf_cfg *cfg)
613 {
614 int ret = 0;
615 uint32_t totalsz = 0;
616 uint32_t u = 0;
617
618 LOG_DBG("%s", __func__);
619
620 if ((dev == NULL) || (cfg == NULL)) {
621 return -EINVAL;
622 }
623
624 const struct espi_saf_xec_config * const xcfg = dev->config;
625 struct mchp_espi_saf * const regs = xcfg->saf_base;
626 struct mchp_espi_saf_comm * const comm_regs = xcfg->saf_comm_base;
627 const struct espi_saf_hw_cfg *hwcfg = &cfg->hwcfg;
628 const struct espi_saf_flash_cfg *fcfg = cfg->flash_cfgs;
629
630 if ((fcfg == NULL) || (cfg->nflash_devices == 0U) ||
631 (cfg->nflash_devices > MCHP_SAF_MAX_FLASH_DEVICES)) {
632 return -EINVAL;
633 }
634
635 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) {
636 return -EAGAIN;
637 }
638
639 saf_qmspi_init(xcfg, cfg);
640
641 regs->SAF_CS0_CFG_P2M = 0;
642 regs->SAF_CS1_CFG_P2M = 0;
643
644 regs->SAF_FL_CFG_GEN_DESCR = MCHP_SAF_FL_CFG_GEN_DESCR_STD;
645
646 /* global flash power down activity counter and interval time */
647 regs->SAF_AC_RELOAD = hwcfg->flash_pd_timeout;
648 regs->SAF_FL_PWR_TMOUT = hwcfg->flash_pd_min_interval;
649
650 /* flash device connected to CS0 required */
651 totalsz = fcfg->flashsz;
652 regs->SAF_FL_CFG_THRH = totalsz;
653 ret = saf_flash_cfg(dev, fcfg, 0);
654 if (ret) {
655 return ret;
656 }
657
658 /* optional second flash device connected to CS1 */
659 if (cfg->nflash_devices > 1) {
660 fcfg++;
661 totalsz += fcfg->flashsz;
662 }
663 /* Program CS1 configuration (same as CS0 if only one device) */
664 ret = saf_flash_cfg(dev, fcfg, 1);
665 if (ret) {
666 return ret;
667 }
668
669 if (totalsz == 0) {
670 return -EAGAIN;
671 }
672
673 regs->SAF_FL_CFG_SIZE_LIM = totalsz - 1;
674
675 LOG_DBG("SAF_FL_CFG_THRH = %x SAF_FL_CFG_SIZE_LIM = %x",
676 regs->SAF_FL_CFG_THRH, regs->SAF_FL_CFG_SIZE_LIM);
677
678 saf_tagmap_init(regs, cfg);
679
680 saf_protection_regions_init(regs);
681
682 saf_dnx_bypass_init(regs);
683
684 saf_flash_timing_init(regs, xcfg);
685
686 ret = saf_init_erase_block_size(dev, cfg);
687 if (ret != 0) {
688 LOG_ERR("SAF Config bad flash erase config");
689 return ret;
690 }
691
692 /* Default or expedited prefetch? */
693 u = MCHP_SAF_FL_CFG_MISC_PFOE_DFLT;
694 if (cfg->hwcfg.flags & MCHP_SAF_HW_CFG_FLAG_PFEXP) {
695 u = MCHP_SAF_FL_CFG_MISC_PFOE_EXP;
696 }
697
698 regs->SAF_FL_CFG_MISC =
699 (regs->SAF_FL_CFG_MISC & ~(MCHP_SAF_FL_CFG_MISC_PFOE_MASK)) | u;
700
701 /* enable prefetch ? */
702 if (cfg->hwcfg.flags & MCHP_SAF_HW_CFG_FLAG_PFEN) {
703 comm_regs->SAF_COMM_MODE |= MCHP_SAF_COMM_MODE_PF_EN;
704 } else {
705 comm_regs->SAF_COMM_MODE &= ~(MCHP_SAF_COMM_MODE_PF_EN);
706 }
707
708 LOG_DBG("%s SAF_FL_CFG_MISC: %x", __func__, regs->SAF_FL_CFG_MISC);
709 LOG_DBG("%s Aft MCHP_SAF_COMM_MODE_REG: %x", __func__,
710 comm_regs->SAF_COMM_MODE);
711
712 saf_qmspi_ldma_cfg(xcfg);
713
714 return 0;
715 }
716
espi_saf_xec_set_pr(const struct device * dev,const struct espi_saf_protection * pr)717 static int espi_saf_xec_set_pr(const struct device *dev,
718 const struct espi_saf_protection *pr)
719 {
720 if ((dev == NULL) || (pr == NULL)) {
721 return -EINVAL;
722 }
723
724 if (pr->nregions >= MCHP_ESPI_SAF_PR_MAX) {
725 return -EINVAL;
726 }
727
728 const struct espi_saf_xec_config * const xcfg = dev->config;
729 struct mchp_espi_saf * const regs = xcfg->saf_base;
730
731 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) {
732 return -EAGAIN;
733 }
734
735 const struct espi_saf_pr *preg = pr->pregions;
736 size_t n = pr->nregions;
737
738 while (n--) {
739 uint8_t regnum = preg->pr_num;
740
741 if (regnum >= MCHP_ESPI_SAF_PR_MAX) {
742 return -EINVAL;
743 }
744
745 /* NOTE: If previously locked writes have no effect */
746 if (preg->flags & MCHP_SAF_PR_FLAG_ENABLE) {
747 regs->SAF_PROT_RG[regnum].START = preg->start >> 12U;
748 regs->SAF_PROT_RG[regnum].LIMIT =
749 (preg->start + preg->size - 1U) >> 12U;
750 regs->SAF_PROT_RG[regnum].WEBM = preg->master_bm_we;
751 regs->SAF_PROT_RG[regnum].RDBM = preg->master_bm_rd;
752 } else {
753 regs->SAF_PROT_RG[regnum].START = 0x7FFFFU;
754 regs->SAF_PROT_RG[regnum].LIMIT = 0U;
755 regs->SAF_PROT_RG[regnum].WEBM = 0U;
756 regs->SAF_PROT_RG[regnum].RDBM = 0U;
757 }
758
759 if (preg->flags & MCHP_SAF_PR_FLAG_LOCK) {
760 regs->SAF_PROT_LOCK |= (1UL << regnum);
761 }
762
763 preg++;
764 }
765
766 return 0;
767 }
768
espi_saf_xec_channel_ready(const struct device * dev)769 static bool espi_saf_xec_channel_ready(const struct device *dev)
770 {
771 const struct espi_saf_xec_config * const xcfg = dev->config;
772 struct mchp_espi_saf * const regs = xcfg->saf_base;
773
774 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) {
775 return true;
776 }
777
778 return false;
779 }
780
781 /*
782 * MCHP SAF hardware supports a range of flash block erase
783 * sizes from 1KB to 128KB. The eSPI Host specification requires
784 * 4KB must be supported. The MCHP SAF QMSPI HW interface only
785 * supported three erase sizes. Most SPI flash devices chosen for
786 * SAF support 4KB, 32KB, and 64KB.
787 * Get flash erase sizes driver has configured from eSPI capabilities
788 * registers. We assume driver flash tables have opcodes to match
789 * capabilities configuration.
790 * Check requested erase size is supported.
791 */
792 struct erase_size_encoding {
793 uint8_t hwbitpos;
794 uint8_t encoding;
795 };
796
797 static const struct erase_size_encoding ersz_enc[] = {
798 { MCHP_ESPI_SERASE_SZ_4K_BITPOS, 0 },
799 { MCHP_ESPI_SERASE_SZ_32K_BITPOS, 1 },
800 { MCHP_ESPI_SERASE_SZ_64K_BITPOS, 2 }
801 };
802
803 #define SAF_ERASE_ENCODING_MAX_ENTRY \
804 (sizeof(ersz_enc) / sizeof(struct erase_size_encoding))
805
get_erase_size_encoding(const struct device * dev,uint32_t erase_size)806 static uint32_t get_erase_size_encoding(const struct device *dev, uint32_t erase_size)
807 {
808 const struct espi_saf_xec_config * const xcfg = dev->config;
809 struct espi_iom_regs * const espi_iom = xcfg->iom_base;
810 uint8_t supsz = espi_iom->SAFEBS;
811
812 LOG_DBG("%s\n", __func__);
813 for (int i = 0; i < SAF_ERASE_ENCODING_MAX_ENTRY; i++) {
814 uint32_t sz = MCHP_ESPI_SERASE_SZ(ersz_enc[i].hwbitpos);
815
816 if ((sz == erase_size) &&
817 (supsz & (1 << ersz_enc[i].hwbitpos))) {
818 return ersz_enc[i].encoding;
819 }
820 }
821
822 return 0xffffffffU;
823 }
824
check_ecp_access_size(uint32_t reqlen)825 static int check_ecp_access_size(uint32_t reqlen)
826 {
827 if ((reqlen < MCHP_SAF_ECP_CMD_RW_LEN_MIN) ||
828 (reqlen > MCHP_SAF_ECP_CMD_RW_LEN_MAX)) {
829 return -EAGAIN;
830 }
831
832 return 0;
833 }
834
835 /*
836 * EC access to SAF atttached flash array
837 * Allowed commands:
838 * MCHP_SAF_ECP_CMD_READ(0x0), MCHP_SAF_ECP_CMD_WRITE(0x01),
839 * MCHP_SAF_ECP_CMD_ERASE(0x02), MCHP_SAF_ECP_CMD_RPMC_OP1_CS0(0x03),
840 * MCHP_SAF_ECP_CMD_RPMC_OP2_CS0(0x04), MCHP_SAF_ECP_CMD_RPMC_OP1_CS1(0x83),
841 * MCHP_SAF_ECP_CMD_RPMC_OP2_CS1(0x84)
842 */
saf_ecp_access(const struct device * dev,struct espi_saf_packet * pckt,uint8_t cmd)843 static int saf_ecp_access(const struct device *dev,
844 struct espi_saf_packet *pckt, uint8_t cmd)
845 {
846 uint32_t scmd, err_mask, n;
847 int rc, counter;
848 struct espi_saf_xec_data *xdat = dev->data;
849 const struct espi_saf_xec_config * const xcfg = dev->config;
850 struct mchp_espi_saf * const regs = xcfg->saf_base;
851 const struct espi_xec_irq_info *safirq = &xcfg->irq_info_list[0];
852
853 counter = 0;
854 err_mask = MCHP_SAF_ECP_STS_ERR_MASK;
855
856 LOG_DBG("%s", __func__);
857
858 if (!(regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN)) {
859 LOG_ERR("SAF is disabled");
860 return -EIO;
861 }
862
863 n = regs->SAF_ECP_BUSY;
864 if (n & (MCHP_SAF_ECP_EC0_BUSY | MCHP_SAF_ECP_EC1_BUSY)) {
865 LOG_ERR("SAF EC Portal is busy: 0x%08x", n);
866 return -EBUSY;
867 }
868
869 switch (cmd) {
870 case MCHP_SAF_ECP_CMD_READ:
871 case MCHP_SAF_ECP_CMD_WRITE:
872 rc = check_ecp_access_size(pckt->len);
873 if (rc) {
874 LOG_ERR("SAF EC Portal size out of bounds");
875 return rc;
876 }
877
878 if (cmd == MCHP_SAF_ECP_CMD_WRITE) {
879 memcpy(slave_mem, pckt->buf, pckt->len);
880 }
881
882 n = pckt->len;
883 break;
884 case MCHP_SAF_ECP_CMD_ERASE:
885 n = get_erase_size_encoding(dev, pckt->len);
886 if (n == UINT32_MAX) {
887 LOG_ERR("SAF EC Portal unsupported erase size");
888 return -EAGAIN;
889 }
890 break;
891 case MCHP_SAF_ECP_CMD_RPMC_OP1_CS0:
892 case MCHP_SAF_ECP_CMD_RPMC_OP2_CS0:
893 rc = check_ecp_access_size(pckt->len);
894 if (rc) {
895 LOG_ERR("SAF EC Portal RPMC size out of bounds");
896 return rc;
897 }
898 if (!(regs->SAF_CFG_CS0_OPD & SAF_CFG_CS_OPC_RPMC_OP2_MSK)) {
899 LOG_ERR("SAF CS0 RPMC opcode not configured");
900 return -EIO;
901 }
902 n = pckt->len;
903 break;
904 case MCHP_SAF_ECP_CMD_RPMC_OP1_CS1:
905 case MCHP_SAF_ECP_CMD_RPMC_OP2_CS1:
906 rc = check_ecp_access_size(pckt->len);
907 if (rc) {
908 LOG_ERR("SAF EC Portal RPMC size out of bounds");
909 return rc;
910 }
911 if (!(regs->SAF_CFG_CS1_OPD & SAF_CFG_CS_OPC_RPMC_OP2_MSK)) {
912 LOG_ERR("SAF CS1 RPMC opcode not configured");
913 return -EIO;
914 }
915 n = pckt->len;
916 break;
917 default:
918 LOG_ERR("SAF EC Portal bad cmd");
919 return -EAGAIN;
920 }
921
922 LOG_DBG("%s params val done", __func__);
923
924 regs->SAF_ECP_INTEN = 0;
925 regs->SAF_ECP_STATUS = MCHP_SAF_ECP_STS_MASK;
926 mchp_xec_ecia_girq_src_clr(safirq->gid, safirq->gpos);
927
928 regs->SAF_ECP_INTEN = BIT(MCHP_SAF_ECP_INTEN_DONE_POS);
929
930 regs->SAF_ECP_FLAR = pckt->flash_addr;
931 regs->SAF_ECP_BFAR = (uint32_t)&slave_mem[0];
932
933 scmd = MCHP_SAF_ECP_CMD_PUT_FLASH_NP |
934 ((uint32_t)cmd << MCHP_SAF_ECP_CMD_CTYPE_POS) |
935 ((n << MCHP_SAF_ECP_CMD_LEN_POS) & MCHP_SAF_ECP_CMD_LEN_MASK);
936
937 LOG_DBG("%s ECP_FLAR=0x%x", __func__, regs->SAF_ECP_FLAR);
938 LOG_DBG("%s ECP_BFAR=0x%x", __func__, regs->SAF_ECP_BFAR);
939 LOG_DBG("%s ECP_CMD=0x%x", __func__, scmd);
940
941 regs->SAF_ECP_CMD = scmd;
942 regs->SAF_ECP_START = MCHP_SAF_ECP_START;
943
944 rc = k_sem_take(&xdat->ecp_lock, K_MSEC(MAX_SAF_FLASH_TIMEOUT_MS));
945 if (rc == -EAGAIN) {
946 LOG_ERR("%s timeout", __func__);
947 return -ETIMEDOUT;
948 }
949
950 LOG_DBG("%s wake on semaphore", __func__);
951
952 n = regs->SAF_ECP_STATUS;
953 /* clear hardware status and check for errors */
954 if (n & err_mask) {
955 regs->SAF_ECP_STATUS = n;
956 LOG_ERR("%s error %x", __func__, n);
957 return -EIO;
958 }
959
960 if (cmd == MCHP_SAF_ECP_CMD_READ) {
961 memcpy(pckt->buf, slave_mem, pckt->len);
962 }
963
964 return rc;
965 }
966
967 /* Flash read using SAF EC Portal */
saf_xec_flash_read(const struct device * dev,struct espi_saf_packet * pckt)968 static int saf_xec_flash_read(const struct device *dev,
969 struct espi_saf_packet *pckt)
970 {
971 LOG_DBG("%s", __func__);
972 return saf_ecp_access(dev, pckt, MCHP_SAF_ECP_CMD_READ);
973 }
974
975 /* Flash write using SAF EC Portal */
saf_xec_flash_write(const struct device * dev,struct espi_saf_packet * pckt)976 static int saf_xec_flash_write(const struct device *dev,
977 struct espi_saf_packet *pckt)
978 {
979 return saf_ecp_access(dev, pckt, MCHP_SAF_ECP_CMD_WRITE);
980 }
981
982 /* Flash erase using SAF EC Portal */
saf_xec_flash_erase(const struct device * dev,struct espi_saf_packet * pckt)983 static int saf_xec_flash_erase(const struct device *dev,
984 struct espi_saf_packet *pckt)
985 {
986 return saf_ecp_access(dev, pckt, MCHP_SAF_ECP_CMD_ERASE);
987 }
988
espi_saf_xec_manage_callback(const struct device * dev,struct espi_callback * callback,bool set)989 static int espi_saf_xec_manage_callback(const struct device *dev,
990 struct espi_callback *callback,
991 bool set)
992 {
993 struct espi_saf_xec_data *data = dev->data;
994
995 return espi_manage_callback(&data->callbacks, callback, set);
996 }
997
espi_saf_xec_activate(const struct device * dev)998 static int espi_saf_xec_activate(const struct device *dev)
999 {
1000 if (dev == NULL) {
1001 return -EINVAL;
1002 }
1003
1004 const struct espi_saf_xec_config * const xcfg = dev->config;
1005 struct mchp_espi_saf * const regs = xcfg->saf_base;
1006 const struct espi_xec_irq_info *safirq = &xcfg->irq_info_list[1];
1007
1008 regs->SAF_ESPI_MON_STATUS = MCHP_SAF_ESPI_MON_STS_IEN_MSK;
1009 mchp_xec_ecia_girq_src_clr(safirq->gid, safirq->gpos);
1010
1011 regs->SAF_FL_CFG_MISC |= MCHP_SAF_FL_CFG_MISC_SAF_EN;
1012 regs->SAF_ESPI_MON_INTEN = (BIT(MCHP_SAF_ESPI_MON_STS_IEN_TMOUT_POS) |
1013 BIT(MCHP_SAF_ESPI_MON_STS_IEN_OOR_POS) |
1014 BIT(MCHP_SAF_ESPI_MON_STS_IEN_AV_POS) |
1015 BIT(MCHP_SAF_ESPI_MON_STS_IEN_BND_4K_POS) |
1016 BIT(MCHP_SAF_ESPI_MON_STS_IEN_ERSZ_POS));
1017
1018 k_busy_wait(1000); /* TODO FIXME get estimate of time interval */
1019
1020 return 0;
1021 }
1022
espi_saf_done_isr(const struct device * dev)1023 static void espi_saf_done_isr(const struct device *dev)
1024 {
1025 const struct espi_saf_xec_config * const xcfg = dev->config;
1026 struct espi_saf_xec_data *data = dev->data;
1027 struct mchp_espi_saf * const regs = xcfg->saf_base;
1028 const struct espi_xec_irq_info *safirq = &xcfg->irq_info_list[0];
1029 uint32_t ecp_status = regs->SAF_ECP_STATUS;
1030 struct espi_event evt = { .evt_type = ESPI_BUS_SAF_NOTIFICATION,
1031 .evt_details = BIT(0),
1032 .evt_data = ecp_status };
1033
1034 regs->SAF_ECP_INTEN = 0u;
1035 regs->SAF_ECP_STATUS = BIT(MCHP_SAF_ECP_STS_DONE_POS);
1036 mchp_xec_ecia_girq_src_clr(safirq->gid, safirq->gpos);
1037
1038 data->hwstatus = ecp_status;
1039
1040 LOG_DBG("SAF Done ISR: status=0x%x", ecp_status);
1041
1042 espi_send_callbacks(&data->callbacks, dev, evt);
1043
1044 k_sem_give(&data->ecp_lock);
1045 }
1046
espi_saf_err_isr(const struct device * dev)1047 static void espi_saf_err_isr(const struct device *dev)
1048 {
1049 const struct espi_saf_xec_config * const xcfg = dev->config;
1050 struct espi_saf_xec_data *data = dev->data;
1051 struct mchp_espi_saf * const regs = xcfg->saf_base;
1052 const struct espi_xec_irq_info *safirq = &xcfg->irq_info_list[1];
1053 uint32_t mon_status = regs->SAF_ESPI_MON_STATUS;
1054 struct espi_event evt = { .evt_type = ESPI_BUS_PERIPHERAL_NOTIFICATION,
1055 .evt_details = BIT(7),
1056 .evt_data = mon_status };
1057
1058 regs->SAF_ESPI_MON_STATUS = mon_status;
1059 mchp_xec_ecia_girq_src_clr(safirq->gid, safirq->gpos);
1060
1061 data->hwstatus = mon_status;
1062 espi_send_callbacks(&data->callbacks, dev, evt);
1063 }
1064
1065 static const struct espi_saf_driver_api espi_saf_xec_driver_api = {
1066 .config = espi_saf_xec_configuration,
1067 .set_protection_regions = espi_saf_xec_set_pr,
1068 .activate = espi_saf_xec_activate,
1069 .get_channel_status = espi_saf_xec_channel_ready,
1070 .flash_read = saf_xec_flash_read,
1071 .flash_write = saf_xec_flash_write,
1072 .flash_erase = saf_xec_flash_erase,
1073 .manage_callback = espi_saf_xec_manage_callback,
1074 };
1075
espi_saf_xec_init(const struct device * dev)1076 static int espi_saf_xec_init(const struct device *dev)
1077 {
1078 const struct espi_saf_xec_config * const xcfg = dev->config;
1079 struct espi_saf_xec_data * const data = dev->data;
1080 struct espi_iom_regs * const espi_iom = xcfg->iom_base;
1081
1082 /* ungate SAF clocks by disabling PCR sleep enable */
1083 z_mchp_xec_pcr_periph_sleep(xcfg->pcr_idx, xcfg->pcr_pos, 0);
1084
1085 /* Configure the channels and its capabilities based on build config */
1086 espi_iom->CAP0 |= MCHP_ESPI_GBL_CAP0_FC_SUPP;
1087 espi_iom->CAPFC &= ~(MCHP_ESPI_FC_CAP_SHARE_MASK);
1088 espi_iom->CAPFC |= MCHP_ESPI_FC_CAP_SHARE_MAF_SAF;
1089
1090 xcfg->irq_config_func();
1091
1092 k_sem_init(&data->ecp_lock, 0, 1);
1093
1094 return 0;
1095 }
1096
1097
1098 /* n = node-id, p = property, i = index */
1099 #define XEC_SAF_IRQ_INFO(n, p, i) \
1100 { \
1101 .gid = MCHP_XEC_ECIA_GIRQ(DT_PROP_BY_IDX(n, p, i)), \
1102 .gpos = MCHP_XEC_ECIA_GIRQ_POS(DT_PROP_BY_IDX(n, p, i)), \
1103 .anid = MCHP_XEC_ECIA_NVIC_AGGR(DT_PROP_BY_IDX(n, p, i)), \
1104 .dnid = MCHP_XEC_ECIA_NVIC_DIRECT(DT_PROP_BY_IDX(n, p, i)), \
1105 },
1106
1107 #define ESPI_SAF_XEC_DEVICE(n) \
1108 \
1109 static struct espi_saf_xec_data espisaf_xec_data_##n; \
1110 \
1111 static void espi_saf_xec_connect_irqs_##n(void); \
1112 \
1113 static const struct espi_xec_irq_info espi_saf_xec_irq_info_##n[] = { \
1114 DT_INST_FOREACH_PROP_ELEM(n, girqs, XEC_SAF_IRQ_INFO) \
1115 }; \
1116 \
1117 static const struct espi_saf_xec_config espisaf_xec_config_##n = { \
1118 .saf_base = (struct mchp_espi_saf * const)( \
1119 DT_INST_REG_ADDR_BY_IDX(n, 0)), \
1120 .qmspi_base = (struct qmspi_regs * const)( \
1121 DT_INST_REG_ADDR_BY_IDX(n, 1)), \
1122 .saf_comm_base = (struct mchp_espi_saf_comm * const)( \
1123 DT_INST_REG_ADDR_BY_IDX(n, 2)), \
1124 .iom_base = (struct espi_iom_regs * const)( \
1125 DT_REG_ADDR_BY_NAME(DT_INST_PARENT(n), io)), \
1126 .poll_timeout = DT_INST_PROP_OR(n, poll_timeout, \
1127 MCHP_SAF_FLASH_POLL_TIMEOUT), \
1128 .consec_rd_timeout = DT_INST_PROP_OR( \
1129 n, consec_rd_timeout, MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT), \
1130 .sus_chk_delay = DT_INST_PROP_OR(n, sus_chk_delay, \
1131 MCHP_SAF_FLASH_SUS_CHK_DELAY), \
1132 .sus_rsm_interval = DT_INST_PROP_OR(n, sus_rsm_interval, \
1133 MCHP_SAF_FLASH_SUS_RSM_INTERVAL), \
1134 .poll_interval = DT_INST_PROP_OR(n, poll_interval, \
1135 MCHP_SAF_FLASH_POLL_INTERVAL), \
1136 .pcr_idx = DT_INST_PROP_BY_IDX(n, pcrs, 0), \
1137 .pcr_pos = DT_INST_PROP_BY_IDX(n, pcrs, 1), \
1138 .irq_config_func = espi_saf_xec_connect_irqs_##n, \
1139 .irq_info_size = ARRAY_SIZE(espi_saf_xec_irq_info_##n), \
1140 .irq_info_list = espi_saf_xec_irq_info_##n, \
1141 }; \
1142 DEVICE_DT_INST_DEFINE(0, &espi_saf_xec_init, NULL, \
1143 &espisaf_xec_data_##n, \
1144 &espisaf_xec_config_##n, POST_KERNEL, \
1145 CONFIG_ESPI_SAF_INIT_PRIORITY, \
1146 &espi_saf_xec_driver_api); \
1147 \
1148 static void espi_saf_xec_connect_irqs_##n(void) \
1149 { \
1150 uint8_t girq, gpos; \
1151 \
1152 /* SAF Done */ \
1153 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 0, irq), \
1154 DT_INST_IRQ_BY_IDX(n, 0, priority), \
1155 espi_saf_done_isr, \
1156 DEVICE_DT_INST_GET(n), 0); \
1157 irq_enable(DT_INST_IRQ_BY_IDX(n, 0, irq)); \
1158 \
1159 girq = MCHP_XEC_ECIA_GIRQ(DT_INST_PROP_BY_IDX(n, girqs, 0)); \
1160 gpos = MCHP_XEC_ECIA_GIRQ_POS(DT_INST_PROP_BY_IDX(n, girqs, 0)); \
1161 mchp_xec_ecia_girq_src_en(girq, gpos); \
1162 \
1163 /* SAF Error */ \
1164 IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 1, irq), \
1165 DT_INST_IRQ_BY_IDX(n, 1, priority), \
1166 espi_saf_err_isr, \
1167 DEVICE_DT_INST_GET(n), 0); \
1168 irq_enable(DT_INST_IRQ_BY_IDX(n, 1, irq)); \
1169 \
1170 girq = MCHP_XEC_ECIA_GIRQ(DT_INST_PROP_BY_IDX(n, girqs, 1)); \
1171 gpos = MCHP_XEC_ECIA_GIRQ_POS(DT_INST_PROP_BY_IDX(n, girqs, 1)); \
1172 mchp_xec_ecia_girq_src_en(girq, gpos); \
1173 }
1174
1175 DT_INST_FOREACH_STATUS_OKAY(ESPI_SAF_XEC_DEVICE)
1176
