1 /*
2 * Copyright (c) 2021 IoT.bzh
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT renesas_rcar_can
8
9 #include <zephyr/kernel.h>
10 #include <errno.h>
11 #include <zephyr/drivers/can.h>
12 #include <zephyr/drivers/can/transceiver.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
15 #include <zephyr/drivers/pinctrl.h>
16 #include <zephyr/logging/log.h>
17 #include <zephyr/irq.h>
18
19 LOG_MODULE_REGISTER(can_rcar, CONFIG_CAN_LOG_LEVEL);
20
21 /* Control Register */
22 #define RCAR_CAN_CTLR 0x0840
23 /* Control Register bits */
24 #define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */
25 #define RCAR_CAN_CTLR_BOM_ENT BIT(11) /* Automatic halt mode entry at bus-off entry */
26 #define RCAR_CAN_CTLR_SLPM BIT(10)
27 #define RCAR_CAN_CTLR_CANM_HALT BIT(9)
28 #define RCAR_CAN_CTLR_CANM_RESET BIT(8)
29 #define RCAR_CAN_CTLR_CANM_MASK (3 << 8)
30 #define RCAR_CAN_CTLR_MLM BIT(3) /* Message Lost Mode Select */
31 #define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */
32 #define RCAR_CAN_CTLR_IDFM_MIXED BIT(2) /* Mixed ID mode */
33 #define RCAR_CAN_CTLR_MBM BIT(0) /* Mailbox Mode select */
34
35 /* Mask Register */
36 #define RCAR_CAN_MKR0 0x0430
37 #define RCAR_CAN_MKR1 0x0434
38 #define RCAR_CAN_MKR2 0x0400
39 #define RCAR_CAN_MKR3 0x0404
40 #define RCAR_CAN_MKR4 0x0408
41 #define RCAR_CAN_MKR5 0x040C
42 #define RCAR_CAN_MKR6 0x0410
43 #define RCAR_CAN_MKR7 0x0414
44 #define RCAR_CAN_MKR8 0x0418
45 #define RCAR_CAN_MKR9 0x041C
46
47 /* FIFO Received ID Compare Register 0 */
48 #define RCAR_CAN_FIDCR0 0x0420
49
50 /* FIFO Received ID Compare Register 1 */
51 #define RCAR_CAN_FIDCR1 0x0424
52
53 /* FIFO Received ID Compare Registers 0 and 1 bits */
54 #define RCAR_CAN_FIDCR_IDE BIT(31) /* ID Extension Bit */
55 #define RCAR_CAN_FIDCR_RTR BIT(30) /* RTR Bit */
56
57 /* Mask Invalid Register 0 */
58 #define RCAR_CAN_MKIVLR0 0x0438
59 /* Mask Invalid Register 1 */
60 #define RCAR_CAN_MKIVLR1 0x0428
61 /* Mailbox Interrupt Enable Registers*/
62 #define RCAR_CAN_MIER0 0x043C
63 #define RCAR_CAN_MIER1 0x042C
64 #define RCAR_CAN_MIER1_RXFIE BIT(28) /* Rx FIFO Interrupt Enable */
65 #define RCAR_CAN_MIER1_TXFIE BIT(24) /* Tx FIFO Interrupt Enable */
66
67 #define RCAR_CAN_STR 0x0842 /* Status Register */
68 #define RCAR_CAN_STR_RSTST BIT(8) /* Reset Status Bit */
69 #define RCAR_CAN_STR_HLTST BIT(9) /* Halt Status Bit */
70 #define RCAR_CAN_STR_SLPST BIT(10) /* Sleep Status Bit */
71 #define MAX_STR_READS 0x100
72
73 /* Bit Configuration Register */
74 #define RCAR_CAN_BCR 0x0844
75
76 /* Clock Select Register */
77 #define RCAR_CAN_CLKR 0x0847
78 #define RCAR_CAN_CLKR_EXT_CLOCK 0x3 /* External input clock */
79 #define RCAR_CAN_CLKR_CLKP2 0x1
80 #define RCAR_CAN_CLKR_CLKP1 0x0
81
82 /* Error Interrupt Enable Register */
83 #define RCAR_CAN_EIER 0x084C
84
85 /* Interrupt Enable Register */
86 #define RCAR_CAN_IER 0x0860
87 #define RCAR_CAN_IER_ERSIE BIT(5) /* Error Interrupt Enable Bit */
88 #define RCAR_CAN_IER_RXFIE BIT(4) /* Rx FIFO Interrupt Enable Bit */
89 #define RCAR_CAN_IER_TXFIE BIT(3) /* Tx FIFO Interrupt Enable Bit */
90
91 /* Interrupt Status Register */
92 #define RCAR_CAN_ISR 0x0861
93 #define RCAR_CAN_ISR_ERSF BIT(5) /* Error (ERS) Interrupt */
94 #define RCAR_CAN_ISR_RXFF BIT(4) /* Reception FIFO Interrupt */
95 #define RCAR_CAN_ISR_TXFF BIT(3) /* Transmission FIFO Interrupt */
96
97 /* Receive FIFO Control Register */
98 #define RCAR_CAN_RFCR 0x0848
99 #define RCAR_CAN_RFCR_RFE BIT(0) /* Receive FIFO Enable */
100 #define RCAR_CAN_RFCR_RFEST BIT(7) /* Receive FIFO Empty Flag */
101
102 /* Receive FIFO Pointer Control Register */
103 #define RCAR_CAN_RFPCR 0x0849
104
105 /* Transmit FIFO Control Register */
106 #define RCAR_CAN_TFCR 0x084A
107 #define RCAR_CAN_TFCR_TFE BIT(0) /* Transmit FIFO Enable */
108 #define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Msg Number Status Bits */
109 #define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Tx FIFO Unsent */
110
111 /* Transmit FIFO Pointer Control Register */
112 #define RCAR_CAN_TFPCR 0x084B
113
114 /* Error Code Store Register*/
115 #define RCAR_CAN_ECSR 0x0850 /* Error Code Store Register */
116 #define RCAR_CAN_ECSR_EDPM BIT(7) /* Error Display Mode Select */
117 #define RCAR_CAN_ECSR_ADEF BIT(6) /* ACK Delimiter Error Flag */
118 #define RCAR_CAN_ECSR_BE0F BIT(5) /* Bit Error (dominant) Flag */
119 #define RCAR_CAN_ECSR_BE1F BIT(4) /* Bit Error (recessive) Flag */
120 #define RCAR_CAN_ECSR_CEF BIT(3) /* CRC Error Flag */
121 #define RCAR_CAN_ECSR_AEF BIT(2) /* ACK Error Flag */
122 #define RCAR_CAN_ECSR_FEF BIT(1) /* Form Error Flag */
123 #define RCAR_CAN_ECSR_SEF BIT(0) /* Stuff Error Flag */
124
125 /* Test Control Register */
126 #define RCAR_CAN_TCR 0x0858
127 #define RCAR_CAN_TCR_TSTE BIT(0) /* Test Mode Enable Bit*/
128 #define RCAR_CAN_TCR_LISTEN_ONLY BIT(1)
129 #define RCAR_CAN_TCR_INT_LOOP (3 << 1) /* Internal loopback*/
130
131 /* Error Interrupt Factor Judge Register bits */
132 #define RCAR_CAN_EIFR 0x084D
133 #define RCAR_CAN_EIFR_BLIF BIT(7) /* Bus Lock Detect Flag */
134 #define RCAR_CAN_EIFR_OLIF BIT(6) /* Overload Frame Transmission */
135 #define RCAR_CAN_EIFR_ORIF BIT(5) /* Receive Overrun Detect Flag */
136 #define RCAR_CAN_EIFR_BORIF BIT(4) /* Bus-Off Recovery Detect Flag */
137 #define RCAR_CAN_EIFR_BOEIF BIT(3) /* Bus-Off Entry Detect Flag */
138 #define RCAR_CAN_EIFR_EPIF BIT(2) /* Error Passive Detect Flag */
139 #define RCAR_CAN_EIFR_EWIF BIT(1) /* Error Warning Detect Flag */
140 #define RCAR_CAN_EIFR_BEIF BIT(0) /* Bus Error Detect Flag */
141
142 /* Receive Error Count Register */
143 #define RCAR_CAN_RECR 0x084D
144 /* Transmit Error Count Register */
145 #define RCAR_CAN_TECR 0x084F
146
147 /* Mailbox configuration:
148 * mailbox 60 - 63 - Rx FIFO mailboxes
149 * mailbox 56 - 59 - Tx FIFO mailboxes
150 * non-FIFO mailboxes are not used
151 */
152 #define RCAR_CAN_MB_56 0x0380
153 #define RCAR_CAN_MB_60 0x03C0
154 /* DLC must be accessed as a 16 bit register */
155 #define RCAR_CAN_MB_DLC_OFFSET 0x4 /* Data length code */
156 #define RCAR_CAN_MB_DATA_OFFSET 0x6 /* Data section */
157 #define RCAR_CAN_MB_TSH_OFFSET 0x14 /* Timestamp upper byte */
158 #define RCAR_CAN_MB_TSL_OFFSET 0x15 /* Timestamp lower byte */
159 #define RCAR_CAN_FIFO_DEPTH 4
160 #define RCAR_CAN_MB_SID_SHIFT 18
161 #define RCAR_CAN_MB_RTR BIT(30)
162 #define RCAR_CAN_MB_IDE BIT(31)
163 #define RCAR_CAN_MB_SID_MASK 0x1FFC0000
164 #define RCAR_CAN_MB_EID_MASK 0x1FFFFFFF
165
166 typedef void (*init_func_t)(const struct device *dev);
167
168 struct can_rcar_cfg {
169 const struct can_driver_config common;
170 uint32_t reg_addr;
171 int reg_size;
172 init_func_t init_func;
173 const struct device *clock_dev;
174 struct rcar_cpg_clk mod_clk;
175 struct rcar_cpg_clk bus_clk;
176 uint8_t sjw;
177 uint8_t prop_seg;
178 uint8_t phase_seg1;
179 uint8_t phase_seg2;
180 const struct pinctrl_dev_config *pcfg;
181 };
182
183 struct can_rcar_tx_cb {
184 can_tx_callback_t cb;
185 void *cb_arg;
186 };
187
188 struct can_rcar_data {
189 struct can_driver_data common;
190 struct k_mutex inst_mutex;
191 struct k_sem tx_sem;
192 struct can_rcar_tx_cb tx_cb[RCAR_CAN_FIFO_DEPTH];
193 uint8_t tx_head;
194 uint8_t tx_tail;
195 uint8_t tx_unsent;
196 struct k_mutex rx_mutex;
197 can_rx_callback_t rx_callback[CONFIG_CAN_RCAR_MAX_FILTER];
198 void *rx_callback_arg[CONFIG_CAN_RCAR_MAX_FILTER];
199 struct can_filter filter[CONFIG_CAN_RCAR_MAX_FILTER];
200 enum can_state state;
201 };
202
can_rcar_read16(const struct can_rcar_cfg * config,uint32_t offs)203 static inline uint16_t can_rcar_read16(const struct can_rcar_cfg *config,
204 uint32_t offs)
205 {
206 return sys_read16(config->reg_addr + offs);
207 }
208
can_rcar_write16(const struct can_rcar_cfg * config,uint32_t offs,uint16_t value)209 static inline void can_rcar_write16(const struct can_rcar_cfg *config,
210 uint32_t offs, uint16_t value)
211 {
212 sys_write16(value, config->reg_addr + offs);
213 }
214
can_rcar_tx_done(const struct device * dev,uint8_t err)215 static void can_rcar_tx_done(const struct device *dev, uint8_t err)
216 {
217 struct can_rcar_data *data = dev->data;
218 struct can_rcar_tx_cb *tx_cb;
219
220 tx_cb = &data->tx_cb[data->tx_tail];
221 data->tx_tail++;
222 if (data->tx_tail >= RCAR_CAN_FIFO_DEPTH) {
223 data->tx_tail = 0;
224 }
225
226 data->tx_unsent--;
227 tx_cb->cb(dev, err, tx_cb->cb_arg);
228 k_sem_give(&data->tx_sem);
229 }
230
can_rcar_get_error_count(const struct can_rcar_cfg * config,struct can_bus_err_cnt * err_cnt)231 static void can_rcar_get_error_count(const struct can_rcar_cfg *config,
232 struct can_bus_err_cnt *err_cnt)
233 {
234 err_cnt->tx_err_cnt = sys_read8(config->reg_addr + RCAR_CAN_TECR);
235 err_cnt->rx_err_cnt = sys_read8(config->reg_addr + RCAR_CAN_RECR);
236 }
237
can_rcar_state_change(const struct device * dev,uint32_t newstate)238 static void can_rcar_state_change(const struct device *dev, uint32_t newstate)
239 {
240 const struct can_rcar_cfg *config = dev->config;
241 struct can_rcar_data *data = dev->data;
242 const can_state_change_callback_t cb = data->common.state_change_cb;
243 void *state_change_cb_data = data->common.state_change_cb_user_data;
244 struct can_bus_err_cnt err_cnt;
245
246 if (data->state == newstate) {
247 return;
248 }
249
250 LOG_DBG("Can state change new: %u old:%u\n", newstate, data->state);
251
252 data->state = newstate;
253
254 if (cb == NULL) {
255 return;
256 }
257 can_rcar_get_error_count(config, &err_cnt);
258 cb(dev, newstate, err_cnt, state_change_cb_data);
259 }
260
can_rcar_error(const struct device * dev)261 static void can_rcar_error(const struct device *dev)
262 {
263 const struct can_rcar_cfg *config = dev->config;
264 uint8_t eifr, ecsr;
265
266 eifr = sys_read8(config->reg_addr + RCAR_CAN_EIFR);
267
268 if (eifr & RCAR_CAN_EIFR_BEIF) {
269
270 ecsr = sys_read8(config->reg_addr + RCAR_CAN_ECSR);
271 if (ecsr & RCAR_CAN_ECSR_ADEF) {
272 CAN_STATS_ACK_ERROR_INC(dev);
273 sys_write8((uint8_t)~RCAR_CAN_ECSR_ADEF,
274 config->reg_addr + RCAR_CAN_ECSR);
275 }
276 if (ecsr & RCAR_CAN_ECSR_BE0F) {
277 CAN_STATS_BIT0_ERROR_INC(dev);
278 sys_write8((uint8_t)~RCAR_CAN_ECSR_BE0F,
279 config->reg_addr + RCAR_CAN_ECSR);
280 }
281 if (ecsr & RCAR_CAN_ECSR_BE1F) {
282 CAN_STATS_BIT1_ERROR_INC(dev);
283 sys_write8((uint8_t)~RCAR_CAN_ECSR_BE1F,
284 config->reg_addr + RCAR_CAN_ECSR);
285 }
286 if (ecsr & RCAR_CAN_ECSR_CEF) {
287 CAN_STATS_CRC_ERROR_INC(dev);
288 sys_write8((uint8_t)~RCAR_CAN_ECSR_CEF,
289 config->reg_addr + RCAR_CAN_ECSR);
290 }
291 if (ecsr & RCAR_CAN_ECSR_AEF) {
292 CAN_STATS_ACK_ERROR_INC(dev);
293 sys_write8((uint8_t)~RCAR_CAN_ECSR_AEF,
294 config->reg_addr + RCAR_CAN_ECSR);
295 }
296 if (ecsr & RCAR_CAN_ECSR_FEF) {
297 CAN_STATS_FORM_ERROR_INC(dev);
298 sys_write8((uint8_t)~RCAR_CAN_ECSR_FEF,
299 config->reg_addr + RCAR_CAN_ECSR);
300 }
301 if (ecsr & RCAR_CAN_ECSR_SEF) {
302 CAN_STATS_STUFF_ERROR_INC(dev);
303 sys_write8((uint8_t)~RCAR_CAN_ECSR_SEF,
304 config->reg_addr + RCAR_CAN_ECSR);
305 }
306
307 sys_write8((uint8_t)~RCAR_CAN_EIFR_BEIF,
308 config->reg_addr + RCAR_CAN_EIFR);
309 }
310 if (eifr & RCAR_CAN_EIFR_EWIF) {
311 LOG_DBG("Error warning interrupt\n");
312 /* Clear interrupt condition */
313 sys_write8((uint8_t)~RCAR_CAN_EIFR_EWIF,
314 config->reg_addr + RCAR_CAN_EIFR);
315 can_rcar_state_change(dev, CAN_STATE_ERROR_WARNING);
316 }
317 if (eifr & RCAR_CAN_EIFR_EPIF) {
318 LOG_DBG("Error passive interrupt\n");
319 /* Clear interrupt condition */
320 sys_write8((uint8_t)~RCAR_CAN_EIFR_EPIF,
321 config->reg_addr + RCAR_CAN_EIFR);
322 can_rcar_state_change(dev, CAN_STATE_ERROR_PASSIVE);
323 }
324 if (eifr & RCAR_CAN_EIFR_BORIF) {
325 LOG_DBG("Bus-off recovery interrupt\n");
326 sys_write8(RCAR_CAN_IER_ERSIE, config->reg_addr + RCAR_CAN_IER);
327 /* Clear interrupt condition */
328 sys_write8((uint8_t)~RCAR_CAN_EIFR_BORIF,
329 config->reg_addr + RCAR_CAN_EIFR);
330 can_rcar_state_change(dev, CAN_STATE_BUS_OFF);
331 }
332 if (eifr & RCAR_CAN_EIFR_BOEIF) {
333 LOG_DBG("Bus-off entry interrupt\n");
334 sys_write8(RCAR_CAN_IER_ERSIE, config->reg_addr + RCAR_CAN_IER);
335 /* Clear interrupt condition */
336 sys_write8((uint8_t)~RCAR_CAN_EIFR_BOEIF,
337 config->reg_addr + RCAR_CAN_EIFR);
338 can_rcar_state_change(dev, CAN_STATE_BUS_OFF);
339 }
340 if (eifr & RCAR_CAN_EIFR_ORIF) {
341 LOG_DBG("Receive overrun error interrupt\n");
342 CAN_STATS_RX_OVERRUN_INC(dev);
343 sys_write8((uint8_t)~RCAR_CAN_EIFR_ORIF,
344 config->reg_addr + RCAR_CAN_EIFR);
345 }
346 if (eifr & RCAR_CAN_EIFR_OLIF) {
347 LOG_DBG("Overload Frame Transmission error interrupt\n");
348 sys_write8((uint8_t)~RCAR_CAN_EIFR_OLIF,
349 config->reg_addr + RCAR_CAN_EIFR);
350 }
351 if (eifr & RCAR_CAN_EIFR_BLIF) {
352 LOG_DBG("Bus lock detected interrupt\n");
353 sys_write8((uint8_t)~RCAR_CAN_EIFR_BLIF,
354 config->reg_addr + RCAR_CAN_EIFR);
355 }
356 }
357
can_rcar_rx_filter_isr(const struct device * dev,struct can_rcar_data * data,const struct can_frame * frame)358 static void can_rcar_rx_filter_isr(const struct device *dev,
359 struct can_rcar_data *data,
360 const struct can_frame *frame)
361 {
362 struct can_frame tmp_frame;
363 uint8_t i;
364
365 #ifndef CONFIG_CAN_ACCEPT_RTR
366 if ((frame->flags & CAN_FRAME_RTR) != 0U) {
367 return;
368 }
369 #endif /* !CONFIG_CAN_ACCEPT_RTR */
370
371 for (i = 0; i < CONFIG_CAN_RCAR_MAX_FILTER; i++) {
372 if (data->rx_callback[i] == NULL) {
373 continue;
374 }
375
376 if (!can_frame_matches_filter(frame, &data->filter[i])) {
377 continue; /* filter did not match */
378 }
379 /* Make a temporary copy in case the user
380 * modifies the message.
381 */
382 tmp_frame = *frame;
383 data->rx_callback[i](dev, &tmp_frame, data->rx_callback_arg[i]);
384 }
385 }
386
can_rcar_rx_isr(const struct device * dev)387 static void can_rcar_rx_isr(const struct device *dev)
388 {
389 const struct can_rcar_cfg *config = dev->config;
390 struct can_rcar_data *data = dev->data;
391 struct can_frame frame = {0};
392 uint32_t val;
393 int i;
394
395 val = sys_read32(config->reg_addr + RCAR_CAN_MB_60);
396 if (val & RCAR_CAN_MB_IDE) {
397 frame.flags |= CAN_FRAME_IDE;
398 frame.id = val & RCAR_CAN_MB_EID_MASK;
399 } else {
400 frame.id = (val & RCAR_CAN_MB_SID_MASK) >> RCAR_CAN_MB_SID_SHIFT;
401 }
402
403 frame.dlc = sys_read16(config->reg_addr +
404 RCAR_CAN_MB_60 + RCAR_CAN_MB_DLC_OFFSET) & 0xF;
405
406 /* Be paranoid doc states that any value greater than 8
407 * should be considered as 8 bytes.
408 */
409 if (frame.dlc > CAN_MAX_DLC) {
410 frame.dlc = CAN_MAX_DLC;
411 }
412
413 if (val & RCAR_CAN_MB_RTR) {
414 frame.flags |= CAN_FRAME_RTR;
415 } else {
416 for (i = 0; i < frame.dlc; i++) {
417 frame.data[i] = sys_read8(config->reg_addr +
418 RCAR_CAN_MB_60 + RCAR_CAN_MB_DATA_OFFSET + i);
419 }
420 }
421 #if defined(CONFIG_CAN_RX_TIMESTAMP)
422 /* read upper byte */
423 frame.timestamp = sys_read8(config->reg_addr +
424 RCAR_CAN_MB_60 + RCAR_CAN_MB_TSH_OFFSET) << 8;
425 /* and then read lower byte */
426 frame.timestamp |= sys_read8(config->reg_addr +
427 RCAR_CAN_MB_60 + RCAR_CAN_MB_TSL_OFFSET);
428 #endif
429 /* Increment CPU side pointer */
430 sys_write8(0xff, config->reg_addr + RCAR_CAN_RFPCR);
431
432 can_rcar_rx_filter_isr(dev, data, &frame);
433 }
434
can_rcar_isr(const struct device * dev)435 static void can_rcar_isr(const struct device *dev)
436 {
437 const struct can_rcar_cfg *config = dev->config;
438 struct can_rcar_data *data = dev->data;
439 uint8_t isr, unsent;
440
441 isr = sys_read8(config->reg_addr + RCAR_CAN_ISR);
442 if (isr & RCAR_CAN_ISR_ERSF) {
443 /* Clear the Error interrupt */
444 isr &= ~RCAR_CAN_ISR_ERSF;
445 sys_write8(isr, config->reg_addr + RCAR_CAN_ISR);
446 can_rcar_error(dev);
447 }
448 if (isr & RCAR_CAN_ISR_TXFF) {
449 /* Check for sent messages */
450 while (1) {
451 unsent = sys_read8(config->reg_addr + RCAR_CAN_TFCR);
452 unsent = (unsent & RCAR_CAN_TFCR_TFUST) >>
453 RCAR_CAN_TFCR_TFUST_SHIFT;
454 if (data->tx_unsent <= unsent) {
455 break;
456 }
457 can_rcar_tx_done(dev, 0);
458 }
459
460 /* Clear the Tx interrupt */
461 isr = sys_read8(config->reg_addr + RCAR_CAN_ISR);
462 isr &= ~RCAR_CAN_ISR_TXFF;
463 sys_write8(isr, config->reg_addr + RCAR_CAN_ISR);
464 }
465 if (isr & RCAR_CAN_ISR_RXFF) {
466 /* while there is unread messages */
467 while (!(sys_read8(config->reg_addr + RCAR_CAN_RFCR)
468 & RCAR_CAN_RFCR_RFEST)) {
469 can_rcar_rx_isr(dev);
470 }
471 /* Clear the Rx interrupt */
472 isr = sys_read8(config->reg_addr + RCAR_CAN_ISR);
473 isr &= ~RCAR_CAN_ISR_RXFF;
474 sys_write8(isr, config->reg_addr + RCAR_CAN_ISR);
475 }
476 }
477
can_rcar_leave_sleep_mode(const struct can_rcar_cfg * config)478 static int can_rcar_leave_sleep_mode(const struct can_rcar_cfg *config)
479 {
480 uint16_t ctlr, str;
481 int i;
482
483 ctlr = can_rcar_read16(config, RCAR_CAN_CTLR);
484 ctlr &= ~RCAR_CAN_CTLR_SLPM;
485 can_rcar_write16(config, RCAR_CAN_CTLR, ctlr);
486 for (i = 0; i < MAX_STR_READS; i++) {
487 str = can_rcar_read16(config, RCAR_CAN_STR);
488 if (!(str & RCAR_CAN_STR_SLPST)) {
489 return 0;
490 }
491 }
492 return -EAGAIN;
493 }
494
can_rcar_enter_reset_mode(const struct can_rcar_cfg * config,bool force)495 static int can_rcar_enter_reset_mode(const struct can_rcar_cfg *config, bool force)
496 {
497 uint16_t ctlr;
498 int i;
499
500 ctlr = can_rcar_read16(config, RCAR_CAN_CTLR);
501 ctlr &= ~RCAR_CAN_CTLR_CANM_MASK;
502 ctlr |= RCAR_CAN_CTLR_CANM_RESET;
503 if (force) {
504 ctlr |= RCAR_CAN_CTLR_CANM_HALT;
505 }
506 can_rcar_write16(config, RCAR_CAN_CTLR, ctlr);
507 for (i = 0; i < MAX_STR_READS; i++) {
508 if (can_rcar_read16(config, RCAR_CAN_STR) & RCAR_CAN_STR_RSTST) {
509 return 0;
510 }
511 }
512 return -EAGAIN;
513 }
514
can_rcar_enter_halt_mode(const struct can_rcar_cfg * config)515 static int can_rcar_enter_halt_mode(const struct can_rcar_cfg *config)
516 {
517 uint16_t ctlr;
518 int i;
519
520 ctlr = can_rcar_read16(config, RCAR_CAN_CTLR);
521 ctlr &= ~RCAR_CAN_CTLR_CANM_MASK;
522 ctlr |= RCAR_CAN_CTLR_CANM_HALT;
523 can_rcar_write16(config, RCAR_CAN_CTLR, ctlr);
524
525 /* Wait for controller to apply high bit timing settings */
526 k_usleep(1);
527
528 for (i = 0; i < MAX_STR_READS; i++) {
529 if (can_rcar_read16(config, RCAR_CAN_STR) & RCAR_CAN_STR_HLTST) {
530 return 0;
531 }
532 }
533
534 return -EAGAIN;
535 }
536
can_rcar_enter_operation_mode(const struct can_rcar_cfg * config)537 static int can_rcar_enter_operation_mode(const struct can_rcar_cfg *config)
538 {
539 uint16_t ctlr, str;
540 int i;
541
542 ctlr = can_rcar_read16(config, RCAR_CAN_CTLR);
543 ctlr &= ~RCAR_CAN_CTLR_CANM_MASK;
544 can_rcar_write16(config, RCAR_CAN_CTLR, ctlr);
545
546 /* Wait for controller to apply high bit timing settings */
547 k_usleep(1);
548
549 for (i = 0; i < MAX_STR_READS; i++) {
550 str = can_rcar_read16(config, RCAR_CAN_STR);
551 if (!(str & RCAR_CAN_CTLR_CANM_MASK)) {
552 break;
553 }
554 }
555
556 if (i == MAX_STR_READS) {
557 return -EAGAIN;
558 }
559
560 /* Enable Rx and Tx FIFO */
561 sys_write8(RCAR_CAN_RFCR_RFE, config->reg_addr + RCAR_CAN_RFCR);
562 sys_write8(RCAR_CAN_TFCR_TFE, config->reg_addr + RCAR_CAN_TFCR);
563
564 return 0;
565 }
566
can_rcar_get_capabilities(const struct device * dev,can_mode_t * cap)567 static int can_rcar_get_capabilities(const struct device *dev, can_mode_t *cap)
568 {
569 ARG_UNUSED(dev);
570
571 *cap = CAN_MODE_NORMAL | CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY;
572
573 return 0;
574 }
575
can_rcar_start(const struct device * dev)576 static int can_rcar_start(const struct device *dev)
577 {
578 const struct can_rcar_cfg *config = dev->config;
579 struct can_rcar_data *data = dev->data;
580 int ret;
581
582 if (data->common.started) {
583 return -EALREADY;
584 }
585
586 if (config->common.phy != NULL) {
587 ret = can_transceiver_enable(config->common.phy, data->common.mode);
588 if (ret != 0) {
589 LOG_ERR("failed to enable CAN transceiver (err %d)", ret);
590 return ret;
591 }
592 }
593
594 k_mutex_lock(&data->inst_mutex, K_FOREVER);
595
596 CAN_STATS_RESET(dev);
597
598 ret = can_rcar_enter_operation_mode(config);
599 if (ret != 0) {
600 LOG_ERR("failed to enter operation mode (err %d)", ret);
601
602 if (config->common.phy != NULL) {
603 /* Attempt to disable the CAN transceiver in case of error */
604 (void)can_transceiver_disable(config->common.phy);
605 }
606 } else {
607 data->common.started = true;
608 }
609
610 k_mutex_unlock(&data->inst_mutex);
611
612 return ret;
613 }
614
can_rcar_stop(const struct device * dev)615 static int can_rcar_stop(const struct device *dev)
616 {
617 const struct can_rcar_cfg *config = dev->config;
618 struct can_rcar_data *data = dev->data;
619 int ret;
620
621 if (!data->common.started) {
622 return -EALREADY;
623 }
624
625 k_mutex_lock(&data->inst_mutex, K_FOREVER);
626
627 ret = can_rcar_enter_halt_mode(config);
628 if (ret != 0) {
629 LOG_ERR("failed to enter halt mode (err %d)", ret);
630 k_mutex_unlock(&data->inst_mutex);
631 return ret;
632 }
633
634 data->common.started = false;
635
636 k_mutex_unlock(&data->inst_mutex);
637
638 if (config->common.phy != NULL) {
639 ret = can_transceiver_disable(config->common.phy);
640 if (ret != 0) {
641 LOG_ERR("failed to disable CAN transceiver (err %d)", ret);
642 return ret;
643 }
644 }
645
646 /* Resetting TX FIFO, emptying it */
647 sys_write8((uint8_t)~RCAR_CAN_TFCR_TFE, config->reg_addr + RCAR_CAN_TFCR);
648 sys_write8(RCAR_CAN_TFCR_TFE, config->reg_addr + RCAR_CAN_TFCR);
649
650 /* Empty TX msgq, returning an error for each message */
651 while (data->tx_unsent) {
652 can_rcar_tx_done(dev, -ENETDOWN);
653 }
654
655 return 0;
656 }
657
can_rcar_set_mode(const struct device * dev,can_mode_t mode)658 static int can_rcar_set_mode(const struct device *dev, can_mode_t mode)
659 {
660 const struct can_rcar_cfg *config = dev->config;
661 struct can_rcar_data *data = dev->data;
662 uint8_t tcr = 0;
663 int ret = 0;
664
665 if ((mode & ~(CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY)) != 0) {
666 LOG_ERR("Unsupported mode: 0x%08x", mode);
667 return -ENOTSUP;
668 }
669
670 if (data->common.started) {
671 return -EBUSY;
672 }
673
674 k_mutex_lock(&data->inst_mutex, K_FOREVER);
675
676 if ((mode & (CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY)) ==
677 (CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY)) {
678 LOG_ERR("Combination of loopback and listenonly modes not supported");
679 ret = -ENOTSUP;
680 goto unlock;
681 } else if ((mode & CAN_MODE_LOOPBACK) != 0) {
682 /* Loopback mode */
683 tcr = RCAR_CAN_TCR_INT_LOOP | RCAR_CAN_TCR_TSTE;
684 } else if ((mode & CAN_MODE_LISTENONLY) != 0) {
685 /* Listen-only mode */
686 tcr = RCAR_CAN_TCR_LISTEN_ONLY | RCAR_CAN_TCR_TSTE;
687 } else {
688 /* Normal mode */
689 tcr = 0;
690 }
691
692 sys_write8(tcr, config->reg_addr + RCAR_CAN_TCR);
693
694 data->common.mode = mode;
695
696 unlock:
697 k_mutex_unlock(&data->inst_mutex);
698
699 return ret;
700 }
701
702 /* Bit Configuration Register settings */
703 #define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20)
704 #define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8)
705 #define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4)
706 #define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07)
707
can_rcar_set_bittiming(const struct can_rcar_cfg * config,const struct can_timing * timing)708 static void can_rcar_set_bittiming(const struct can_rcar_cfg *config,
709 const struct can_timing *timing)
710 {
711 uint32_t bcr;
712
713 bcr = RCAR_CAN_BCR_TSEG1(timing->phase_seg1 + timing->prop_seg - 1) |
714 RCAR_CAN_BCR_BPR(timing->prescaler - 1) |
715 RCAR_CAN_BCR_SJW(timing->sjw - 1) |
716 RCAR_CAN_BCR_TSEG2(timing->phase_seg2 - 1);
717
718 /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access.
719 * All the registers are big-endian but they get byte-swapped on 32-bit
720 * read/write (but not on 8-bit, contrary to the manuals)...
721 */
722 sys_write32((bcr << 8) | RCAR_CAN_CLKR_CLKP2,
723 config->reg_addr + RCAR_CAN_BCR);
724 }
725
can_rcar_set_timing(const struct device * dev,const struct can_timing * timing)726 static int can_rcar_set_timing(const struct device *dev,
727 const struct can_timing *timing)
728 {
729 const struct can_rcar_cfg *config = dev->config;
730 struct can_rcar_data *data = dev->data;
731 int ret = 0;
732
733 struct reg_backup {
734 uint32_t address;
735 uint8_t value;
736 };
737
738 struct reg_backup regs[3] = { { RCAR_CAN_TCR, 0 }, { RCAR_CAN_TFCR, 0 }
739 , { RCAR_CAN_RFCR, 0 } };
740
741 if (data->common.started) {
742 return -EBUSY;
743 }
744
745 k_mutex_lock(&data->inst_mutex, K_FOREVER);
746
747 /* Changing bittiming should be done in reset mode.
748 * Switching to reset mode is resetting loopback mode (TCR),
749 * transmit and receive FIFOs (TFCR and RFCR).
750 * Storing these reg values to restore them once back in halt mode.
751 */
752 for (int i = 0; i < 3; i++) {
753 regs[i].value = sys_read8(config->reg_addr + regs[i].address);
754 }
755
756 /* Switching to reset mode */
757 ret = can_rcar_enter_reset_mode(config, true);
758 if (ret != 0) {
759 goto unlock;
760 }
761
762 /* Setting bit timing */
763 can_rcar_set_bittiming(config, timing);
764
765 /* Restoring registers must be done in halt mode */
766 ret = can_rcar_enter_halt_mode(config);
767 if (ret) {
768 goto unlock;
769 }
770
771 /* Restoring registers */
772 for (int i = 0; i < 3; i++) {
773 sys_write8(regs[i].value, config->reg_addr + regs[i].address);
774 }
775
776 unlock:
777 k_mutex_unlock(&data->inst_mutex);
778 return ret;
779 }
780
can_rcar_set_state_change_callback(const struct device * dev,can_state_change_callback_t cb,void * user_data)781 static void can_rcar_set_state_change_callback(const struct device *dev,
782 can_state_change_callback_t cb,
783 void *user_data)
784 {
785 struct can_rcar_data *data = dev->data;
786
787 data->common.state_change_cb = cb;
788 data->common.state_change_cb_user_data = user_data;
789 }
790
can_rcar_get_state(const struct device * dev,enum can_state * state,struct can_bus_err_cnt * err_cnt)791 static int can_rcar_get_state(const struct device *dev, enum can_state *state,
792 struct can_bus_err_cnt *err_cnt)
793 {
794 const struct can_rcar_cfg *config = dev->config;
795 struct can_rcar_data *data = dev->data;
796
797 if (state != NULL) {
798 if (!data->common.started) {
799 *state = CAN_STATE_STOPPED;
800 } else {
801 *state = data->state;
802 }
803 }
804
805 if (err_cnt != NULL) {
806 can_rcar_get_error_count(config, err_cnt);
807 }
808
809 return 0;
810 }
811
812 #ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
can_rcar_recover(const struct device * dev,k_timeout_t timeout)813 static int can_rcar_recover(const struct device *dev, k_timeout_t timeout)
814 {
815 const struct can_rcar_cfg *config = dev->config;
816 struct can_rcar_data *data = dev->data;
817 int64_t start_time;
818 int ret;
819
820 if (!data->common.started) {
821 return -ENETDOWN;
822 }
823
824 if (data->state != CAN_STATE_BUS_OFF) {
825 return 0;
826 }
827
828 if (k_mutex_lock(&data->inst_mutex, K_FOREVER)) {
829 return -EAGAIN;
830 }
831
832 start_time = k_uptime_ticks();
833 while (data->state == CAN_STATE_BUS_OFF) {
834 ret = can_rcar_enter_operation_mode(config);
835 if (ret != 0) {
836 goto done;
837 }
838
839 if (!K_TIMEOUT_EQ(timeout, K_FOREVER) &&
840 k_uptime_ticks() - start_time >= timeout.ticks) {
841 ret = -EAGAIN;
842 goto done;
843 }
844 }
845
846 done:
847 k_mutex_unlock(&data->inst_mutex);
848 return ret;
849 }
850 #endif /* CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */
851
can_rcar_send(const struct device * dev,const struct can_frame * frame,k_timeout_t timeout,can_tx_callback_t callback,void * user_data)852 static int can_rcar_send(const struct device *dev, const struct can_frame *frame,
853 k_timeout_t timeout, can_tx_callback_t callback,
854 void *user_data)
855 {
856 const struct can_rcar_cfg *config = dev->config;
857 struct can_rcar_data *data = dev->data;
858 struct can_rcar_tx_cb *tx_cb;
859 uint32_t identifier;
860 int i;
861
862 LOG_DBG("Sending %d bytes on %s. "
863 "Id: 0x%x, "
864 "ID type: %s, "
865 "Remote Frame: %s"
866 , frame->dlc, dev->name
867 , frame->id
868 , (frame->flags & CAN_FRAME_IDE) != 0 ?
869 "extended" : "standard"
870 , (frame->flags & CAN_FRAME_RTR) != 0 ? "yes" : "no");
871
872 __ASSERT_NO_MSG(callback != NULL);
873 __ASSERT(frame->dlc == 0U || frame->data != NULL, "Dataptr is null");
874
875 if (frame->dlc > CAN_MAX_DLC) {
876 LOG_ERR("DLC of %d exceeds maximum (%d)",
877 frame->dlc, CAN_MAX_DLC);
878 return -EINVAL;
879 }
880
881 if ((frame->flags & ~(CAN_FRAME_IDE | CAN_FRAME_RTR)) != 0) {
882 LOG_ERR("unsupported CAN frame flags 0x%02x", frame->flags);
883 return -ENOTSUP;
884 }
885
886 if (!data->common.started) {
887 return -ENETDOWN;
888 }
889
890 /* Wait for a slot into the tx FIFO */
891 if (k_sem_take(&data->tx_sem, timeout) != 0) {
892 return -EAGAIN;
893 }
894
895 k_mutex_lock(&data->inst_mutex, K_FOREVER);
896 tx_cb = &data->tx_cb[data->tx_head];
897 tx_cb->cb = callback;
898 tx_cb->cb_arg = user_data;
899
900 data->tx_head++;
901 if (data->tx_head >= RCAR_CAN_FIFO_DEPTH) {
902 data->tx_head = 0;
903 }
904
905 if ((frame->flags & CAN_FRAME_IDE) != 0) {
906 identifier = frame->id | RCAR_CAN_MB_IDE;
907 } else {
908 identifier = frame->id << RCAR_CAN_MB_SID_SHIFT;
909 }
910
911 if ((frame->flags & CAN_FRAME_RTR) != 0) {
912 identifier |= RCAR_CAN_MB_RTR;
913 }
914
915 sys_write32(identifier, config->reg_addr + RCAR_CAN_MB_56);
916
917 sys_write16(frame->dlc, config->reg_addr
918 + RCAR_CAN_MB_56 + RCAR_CAN_MB_DLC_OFFSET);
919
920 if ((frame->flags & CAN_FRAME_RTR) == 0) {
921 for (i = 0; i < frame->dlc; i++) {
922 sys_write8(frame->data[i], config->reg_addr
923 + RCAR_CAN_MB_56 + RCAR_CAN_MB_DATA_OFFSET + i);
924 }
925 }
926
927 compiler_barrier();
928 data->tx_unsent++;
929 /* Start Tx: increment the CPU-side pointer for the transmit FIFO
930 * to the next mailbox location
931 */
932 sys_write8(0xff, config->reg_addr + RCAR_CAN_TFPCR);
933
934 k_mutex_unlock(&data->inst_mutex);
935
936 return 0;
937 }
938
can_rcar_add_rx_filter_unlocked(const struct device * dev,can_rx_callback_t cb,void * cb_arg,const struct can_filter * filter)939 static inline int can_rcar_add_rx_filter_unlocked(const struct device *dev,
940 can_rx_callback_t cb,
941 void *cb_arg,
942 const struct can_filter *filter)
943 {
944 struct can_rcar_data *data = dev->data;
945 int i;
946
947 for (i = 0; i < CONFIG_CAN_RCAR_MAX_FILTER; i++) {
948 if (data->rx_callback[i] == NULL) {
949 data->rx_callback_arg[i] = cb_arg;
950 data->filter[i] = *filter;
951 compiler_barrier();
952 data->rx_callback[i] = cb;
953 return i;
954 }
955 }
956
957 return -ENOSPC;
958 }
959
can_rcar_add_rx_filter(const struct device * dev,can_rx_callback_t cb,void * cb_arg,const struct can_filter * filter)960 static int can_rcar_add_rx_filter(const struct device *dev, can_rx_callback_t cb,
961 void *cb_arg, const struct can_filter *filter)
962 {
963 struct can_rcar_data *data = dev->data;
964 int filter_id;
965
966 if ((filter->flags & ~(CAN_FILTER_IDE)) != 0) {
967 LOG_ERR("unsupported CAN filter flags 0x%02x", filter->flags);
968 return -ENOTSUP;
969 }
970
971 k_mutex_lock(&data->rx_mutex, K_FOREVER);
972 filter_id = can_rcar_add_rx_filter_unlocked(dev, cb, cb_arg, filter);
973 k_mutex_unlock(&data->rx_mutex);
974 return filter_id;
975 }
976
can_rcar_remove_rx_filter(const struct device * dev,int filter_id)977 static void can_rcar_remove_rx_filter(const struct device *dev, int filter_id)
978 {
979 struct can_rcar_data *data = dev->data;
980
981 if (filter_id < 0 || filter_id >= CONFIG_CAN_RCAR_MAX_FILTER) {
982 LOG_ERR("filter ID %d out of bounds", filter_id);
983 return;
984 }
985
986 k_mutex_lock(&data->rx_mutex, K_FOREVER);
987 compiler_barrier();
988 data->rx_callback[filter_id] = NULL;
989 k_mutex_unlock(&data->rx_mutex);
990 }
991
can_rcar_init(const struct device * dev)992 static int can_rcar_init(const struct device *dev)
993 {
994 const struct can_rcar_cfg *config = dev->config;
995 struct can_rcar_data *data = dev->data;
996 struct can_timing timing = { 0 };
997 int ret;
998 uint16_t ctlr;
999
1000 k_mutex_init(&data->inst_mutex);
1001 k_mutex_init(&data->rx_mutex);
1002 k_sem_init(&data->tx_sem, RCAR_CAN_FIFO_DEPTH, RCAR_CAN_FIFO_DEPTH);
1003
1004 data->tx_head = 0;
1005 data->tx_tail = 0;
1006 data->tx_unsent = 0;
1007
1008 memset(data->rx_callback, 0, sizeof(data->rx_callback));
1009 data->state = CAN_STATE_ERROR_ACTIVE;
1010 data->common.state_change_cb = NULL;
1011 data->common.state_change_cb_user_data = NULL;
1012
1013 if (config->common.phy != NULL) {
1014 if (!device_is_ready(config->common.phy)) {
1015 LOG_ERR("CAN transceiver not ready");
1016 return -ENODEV;
1017 }
1018 }
1019
1020 if (!device_is_ready(config->clock_dev)) {
1021 LOG_ERR("clock control device not ready");
1022 return -ENODEV;
1023 }
1024
1025 /* Configure dt provided device signals when available */
1026 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1027 if (ret < 0) {
1028 return ret;
1029 }
1030
1031 /* reset the registers */
1032 ret = clock_control_off(config->clock_dev,
1033 (clock_control_subsys_t)&config->mod_clk);
1034 if (ret < 0) {
1035 return ret;
1036 }
1037
1038 ret = clock_control_on(config->clock_dev,
1039 (clock_control_subsys_t)&config->mod_clk);
1040 if (ret < 0) {
1041 return ret;
1042 }
1043
1044 ret = clock_control_on(config->clock_dev,
1045 (clock_control_subsys_t)&config->bus_clk);
1046 if (ret < 0) {
1047 return ret;
1048 }
1049
1050 ret = can_rcar_enter_reset_mode(config, false);
1051 __ASSERT(!ret, "Fail to set CAN controller to reset mode");
1052 if (ret) {
1053 return ret;
1054 }
1055
1056 ret = can_rcar_leave_sleep_mode(config);
1057 __ASSERT(!ret, "Fail to leave CAN controller from sleep mode");
1058 if (ret) {
1059 return ret;
1060 }
1061
1062 if (config->common.sample_point) {
1063 ret = can_calc_timing(dev, &timing, config->common.bus_speed,
1064 config->common.sample_point);
1065 if (ret == -EINVAL) {
1066 LOG_ERR("Can't find timing for given param");
1067 return -EIO;
1068 }
1069 LOG_DBG("Presc: %d, TS1: %d, TS2: %d",
1070 timing.prescaler, timing.phase_seg1, timing.phase_seg2);
1071 LOG_DBG("Sample-point err : %d", ret);
1072 } else {
1073 timing.sjw = config->sjw;
1074 timing.prop_seg = config->prop_seg;
1075 timing.phase_seg1 = config->phase_seg1;
1076 timing.phase_seg2 = config->phase_seg2;
1077 ret = can_calc_prescaler(dev, &timing, config->common.bus_speed);
1078 if (ret) {
1079 LOG_WRN("Bitrate error: %d", ret);
1080 }
1081 }
1082
1083 ret = can_set_timing(dev, &timing);
1084 if (ret) {
1085 return ret;
1086 }
1087
1088 ret = can_rcar_set_mode(dev, CAN_MODE_NORMAL);
1089 if (ret) {
1090 return ret;
1091 }
1092
1093 ctlr = can_rcar_read16(config, RCAR_CAN_CTLR);
1094 ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */
1095 #ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
1096 ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically at bus-off */
1097 #endif
1098 ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */
1099 ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */
1100 ctlr &= ~RCAR_CAN_CTLR_SLPM; /* Clear CAN Sleep mode */
1101 can_rcar_write16(config, RCAR_CAN_CTLR, ctlr);
1102
1103 /* Accept all SID and EID */
1104 sys_write32(0, config->reg_addr + RCAR_CAN_MKR8);
1105 sys_write32(0, config->reg_addr + RCAR_CAN_MKR9);
1106 /* In FIFO mailbox mode, write "0" to bits 24 to 31 */
1107 sys_write32(0, config->reg_addr + RCAR_CAN_MKIVLR0);
1108 sys_write32(0, config->reg_addr + RCAR_CAN_MKIVLR1);
1109 /* Accept standard and extended ID frames, but not
1110 * remote frame.
1111 */
1112 sys_write32(0, config->reg_addr + RCAR_CAN_FIDCR0);
1113 sys_write32(RCAR_CAN_FIDCR_IDE,
1114 config->reg_addr + RCAR_CAN_FIDCR1);
1115
1116 /* Enable and configure FIFO mailbox interrupts Rx and Tx */
1117 sys_write32(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE,
1118 config->reg_addr + RCAR_CAN_MIER1);
1119
1120 sys_write8(RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE | RCAR_CAN_IER_TXFIE,
1121 config->reg_addr + RCAR_CAN_IER);
1122
1123 /* Accumulate error codes */
1124 sys_write8(RCAR_CAN_ECSR_EDPM, config->reg_addr + RCAR_CAN_ECSR);
1125
1126 /* Enable interrupts for all type of errors */
1127 sys_write8(0xFF, config->reg_addr + RCAR_CAN_EIER);
1128
1129 config->init_func(dev);
1130
1131 return 0;
1132 }
1133
can_rcar_get_core_clock(const struct device * dev,uint32_t * rate)1134 static int can_rcar_get_core_clock(const struct device *dev, uint32_t *rate)
1135 {
1136 const struct can_rcar_cfg *config = dev->config;
1137
1138 *rate = config->bus_clk.rate;
1139 return 0;
1140 }
1141
can_rcar_get_max_filters(const struct device * dev,bool ide)1142 static int can_rcar_get_max_filters(const struct device *dev, bool ide)
1143 {
1144 ARG_UNUSED(ide);
1145
1146 return CONFIG_CAN_RCAR_MAX_FILTER;
1147 }
1148
1149 static const struct can_driver_api can_rcar_driver_api = {
1150 .get_capabilities = can_rcar_get_capabilities,
1151 .start = can_rcar_start,
1152 .stop = can_rcar_stop,
1153 .set_mode = can_rcar_set_mode,
1154 .set_timing = can_rcar_set_timing,
1155 .send = can_rcar_send,
1156 .add_rx_filter = can_rcar_add_rx_filter,
1157 .remove_rx_filter = can_rcar_remove_rx_filter,
1158 .get_state = can_rcar_get_state,
1159 #ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
1160 .recover = can_rcar_recover,
1161 #endif
1162 .set_state_change_callback = can_rcar_set_state_change_callback,
1163 .get_core_clock = can_rcar_get_core_clock,
1164 .get_max_filters = can_rcar_get_max_filters,
1165 .timing_min = {
1166 .sjw = 0x1,
1167 .prop_seg = 0x00,
1168 .phase_seg1 = 0x04,
1169 .phase_seg2 = 0x02,
1170 .prescaler = 0x01
1171 },
1172 .timing_max = {
1173 .sjw = 0x4,
1174 .prop_seg = 0x00,
1175 .phase_seg1 = 0x10,
1176 .phase_seg2 = 0x08,
1177 .prescaler = 0x400
1178 }
1179 };
1180
1181 /* Device Instantiation */
1182 #define CAN_RCAR_INIT(n) \
1183 PINCTRL_DT_INST_DEFINE(n); \
1184 static void can_rcar_##n##_init(const struct device *dev); \
1185 static const struct can_rcar_cfg can_rcar_cfg_##n = { \
1186 .common = CAN_DT_DRIVER_CONFIG_INST_GET(n, 1000000), \
1187 .reg_addr = DT_INST_REG_ADDR(n), \
1188 .reg_size = DT_INST_REG_SIZE(n), \
1189 .init_func = can_rcar_##n##_init, \
1190 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
1191 .mod_clk.module = \
1192 DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
1193 .mod_clk.domain = \
1194 DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
1195 .bus_clk.module = \
1196 DT_INST_CLOCKS_CELL_BY_IDX(n, 1, module), \
1197 .bus_clk.domain = \
1198 DT_INST_CLOCKS_CELL_BY_IDX(n, 1, domain), \
1199 .bus_clk.rate = 40000000, \
1200 .sjw = DT_INST_PROP(n, sjw), \
1201 .prop_seg = DT_INST_PROP_OR(n, prop_seg, 0), \
1202 .phase_seg1 = DT_INST_PROP_OR(n, phase_seg1, 0), \
1203 .phase_seg2 = DT_INST_PROP_OR(n, phase_seg2, 0), \
1204 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
1205 }; \
1206 static struct can_rcar_data can_rcar_data_##n; \
1207 \
1208 CAN_DEVICE_DT_INST_DEFINE(n, can_rcar_init, \
1209 NULL, \
1210 &can_rcar_data_##n, \
1211 &can_rcar_cfg_##n, \
1212 POST_KERNEL, \
1213 CONFIG_CAN_INIT_PRIORITY, \
1214 &can_rcar_driver_api \
1215 ); \
1216 static void can_rcar_##n##_init(const struct device *dev) \
1217 { \
1218 IRQ_CONNECT(DT_INST_IRQN(n), \
1219 0, \
1220 can_rcar_isr, \
1221 DEVICE_DT_INST_GET(n), 0); \
1222 \
1223 irq_enable(DT_INST_IRQN(n)); \
1224 }
1225
1226 DT_INST_FOREACH_STATUS_OKAY(CAN_RCAR_INIT)
1227
