1# Copyright (c) 2022-2023 Intel Corporation 2# SPDX-License-Identifier: Apache-2.0 3 4if BOARD_INTEL_RPL_S_CRB || BOARD_INTEL_RPL_P_CRB 5 6config BOARD 7 default "intel_rpl_p_crb" if BOARD_INTEL_RPL_P_CRB 8 default "intel_rpl_s_crb" if BOARD_INTEL_RPL_S_CRB 9 10config BUILD_OUTPUT_STRIPPED 11 default y 12 13config MP_MAX_NUM_CPUS 14 default 2 15 16# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz 17config SYS_CLOCK_HW_CYCLES_PER_SEC 18 default 1900000000 if APIC_TSC_DEADLINE_TIMER 19 default 1900000000 if APIC_TIMER_TSC 20 default 19200000 21 22if APIC_TIMER 23config APIC_TIMER_IRQ 24 default 24 25config APIC_TIMER_TSC_M 26 default 3 27config APIC_TIMER_TSC_N 28 default 249 29endif 30 31config ACPI 32 default y 33 34if ACPI 35config HEAP_MEM_POOL_ADD_SIZE_ACPI 36 default 64000000 37config MAIN_STACK_SIZE 38 default 320000 39 40if SHELL 41config SHELL_STACK_SIZE 42 default 320000 43endif # SHELL 44endif # ACPI 45 46if DMA 47config DMA_64BIT 48 default y 49config DMA_DW_HW_LLI 50 default n 51config DMA_DW_CHANNEL_COUNT 52 default 2 53endif 54 55config UART_NS16550_INTEL_LPSS_DMA 56 default y if BOARD_INTEL_RPL_S_CRB 57 58if SHELL 59config SHELL_STACK_SIZE 60 default 320000 61endif 62 63endif # BOARD_INTEL_RPL_S_CRB || BOARD_INTEL_RPL_P_CRB 64
