1/*
2 * Copyright 2022-2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <nxp/s32/S32Z27-BGA594-pinctrl.h>
8
9&pinctrl {
10	uart0_default: uart0_default {
11		group1 {
12			pinmux = <PB10_LIN_0_TX>;
13			output-enable;
14		};
15		group2 {
16			pinmux = <PB11_LIN_0_RX>;
17			input-enable;
18		};
19	};
20
21	uart9_default: uart9_default {
22		group1 {
23			pinmux = <PM6_LIN_9_TX>;
24			output-enable;
25		};
26		group2 {
27			pinmux = <PM7_LIN_9_RX>;
28			input-enable;
29		};
30	};
31
32	emdio_default: emdio_default {
33		group1 {
34			pinmux = <(PE10_ETH_MDC_I | PE10_ETH_MDC_O)>;
35			input-enable;
36			output-enable;
37		};
38		group2 {
39			pinmux = <(PE11_ETH_MDIO_I | PE11_ETH_MDIO_O)>;
40			input-enable;
41			output-enable;
42			drive-open-drain;
43		};
44	};
45
46	eth0_default: eth0_default {
47		group1 {
48			pinmux = <PF2_ETH_0_RX_CLK>,
49				<PF3_ETH_0_RGMII_RXCTL>,
50				<PF4_ETH_0_RGMII_RXD_0>,
51				<PF5_ETH_0_RGMII_RXD_1>,
52				<PF6_ETH_0_RGMII_RXD_2>,
53				<PF7_ETH_0_RGMII_RXD_3>;
54			input-enable;
55		};
56		group2 {
57			pinmux = <PE12_ETH_0_RGMII_TXC>,
58				<PE13_ETH_0_RGMII_TXCTL>,
59				<PE14_ETH_0_RGMII_TXD_0>,
60				<PE15_ETH_0_RGMII_TXD_1>,
61				<PF0_ETH_0_RGMII_TXD_2>,
62				<PF1_ETH_0_RGMII_TXD_3>;
63			output-enable;
64		};
65	};
66
67	can0_default: can0_default {
68		group1 {
69			pinmux = <PN2_CANXL_0_RX>;
70			input-enable;
71		};
72		group2 {
73			pinmux = <PN1_CANXL_0_TX>;
74			output-enable;
75		};
76	};
77
78	can1_default: can1_default {
79		group1 {
80			pinmux = <PM11_CANXL_1_RX>;
81			input-enable;
82		};
83		group2 {
84			pinmux = <PM10_CANXL_1_TX>;
85			output-enable;
86		};
87	};
88};
89