1/*
2 * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/g4/stm32g431Xb.dtsi>
9#include <st/g4/stm32g431r(6-8-b)tx-pinctrl.dtsi>
10#include "arduino_r3_connector.dtsi"
11#include "st_morpho_connector.dtsi"
12#include <zephyr/dt-bindings/input/input-event-codes.h>
13
14/ {
15	model = "STMicroelectronics STM32G431RB-NUCLEO board";
16	compatible = "st,stm32g431rb-nucleo";
17
18	chosen {
19		zephyr,console = &lpuart1;
20		zephyr,shell-uart = &lpuart1;
21		zephyr,sram = &sram0;
22		zephyr,flash = &flash0;
23	};
24
25	leds: leds {
26		compatible = "gpio-leds";
27		green_led: led_0 {
28			gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
29			label = "User LD2";
30		};
31	};
32
33	pwmleds {
34		compatible = "pwm-leds";
35
36		green_pwm_led: green_pwm_led {
37			pwms = <&pwm2 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
38		};
39	};
40
41	gpio_keys {
42		compatible = "gpio-keys";
43		user_button: button {
44			label = "User";
45			gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
46			zephyr,code = <INPUT_KEY_0>;
47		};
48	};
49
50	aliases {
51		led0 = &green_led;
52		pwm-led0 = &green_pwm_led;
53		sw0 = &user_button;
54		watchdog0 = &iwdg;
55	};
56};
57
58&clk_lsi {
59	status = "okay";
60};
61
62&clk_lse {
63	status = "okay";
64};
65
66&clk_hsi48 {
67	status = "okay";
68};
69
70&clk_hse {
71	clock-frequency = <DT_FREQ_M(24)>;
72	status = "okay";
73};
74
75&pll {
76	div-m = <6>;
77	mul-n = <85>;
78	div-p = <7>;
79	div-q = <2>;
80	div-r = <2>;
81	clocks = <&clk_hse>;
82	status = "okay";
83};
84
85&rcc {
86	clocks = <&pll>;
87	clock-frequency = <DT_FREQ_M(170)>;
88	ahb-prescaler = <1>;
89	apb1-prescaler = <1>;
90	apb2-prescaler = <1>;
91};
92
93&rng {
94	clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x04000000>,
95		 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
96	status = "okay";
97};
98
99&usart1 {
100	pinctrl-0 = <&usart1_tx_pc4 &usart1_rx_pc5>;
101	pinctrl-names = "default";
102	current-speed = <115200>;
103	status = "okay";
104};
105
106&lpuart1 {
107	pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>;
108	pinctrl-names = "default";
109	current-speed = <115200>;
110	status = "okay";
111};
112
113&i2c1 {
114	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
115	pinctrl-names = "default";
116	status = "okay";
117};
118
119&spi1 {
120	pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
121	pinctrl-names = "default";
122	cs-gpios = <&gpiob 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
123	status = "okay";
124};
125
126&spi2 {
127	pinctrl-0 = <&spi2_nss_pb12 &spi2_sck_pb13
128		     &spi2_miso_pb14 &spi2_mosi_pb15>;
129	pinctrl-names = "default";
130	status = "okay";
131};
132
133&spi3 {
134	/* SPI3 on the ST Morpho Connector CN7 pins 17, 1, 2, 3*/
135	pinctrl-0 = <&spi3_nss_pa15 &spi3_sck_pc10
136		     &spi3_miso_pc11 &spi3_mosi_pc12>;
137	pinctrl-names = "default";
138	status = "okay";
139};
140
141&timers2 {
142	status = "okay";
143
144	pwm2: pwm {
145		status = "okay";
146		pinctrl-0 = <&tim2_ch1_pa5>;
147		pinctrl-names = "default";
148	};
149};
150
151stm32_lp_tick_source: &lptim1 {
152	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
153		 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
154	status = "okay";
155};
156
157&rtc {
158	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
159		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
160	status = "okay";
161};
162
163&flash0 {
164
165	partitions {
166		compatible = "fixed-partitions";
167		#address-cells = <1>;
168		#size-cells = <1>;
169
170		/* Set 4Kb of storage at the end of the 128Kb of flash */
171		storage_partition: partition@1f000 {
172			label = "storage";
173			reg = <0x0001f000 DT_SIZE_K(4)>;
174		};
175	};
176};
177
178&iwdg {
179	status = "okay";
180};
181
182&dac1 {
183	status = "okay";
184	pinctrl-0 = <&dac1_out1_pa4>;
185	pinctrl-names = "default";
186};
187