1/* 2 * Copyright (c) 2018, NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7/dts-v1/; 8 9#include <nxp/nxp_rt1020.dtsi> 10#include "mimxrt1020_evk-pinctrl.dtsi" 11#include <zephyr/dt-bindings/input/input-event-codes.h> 12 13/ { 14 model = "NXP MIMXRT1020-EVK board"; 15 compatible = "nxp,mimxrt1021"; 16 17 aliases { 18 led0 = &green_led; 19 sw0 = &user_button; 20 sdhc0 = &usdhc1; 21 }; 22 23 chosen { 24 zephyr,flash-controller = &is25wp064; 25 zephyr,flash = &is25wp064; 26 zephyr,code-partition = &slot0_partition; 27 zephyr,sram = &sdram0; 28 zephyr,itcm = &itcm; 29 zephyr,dtcm = &dtcm; 30 zephyr,console = &lpuart1; 31 zephyr,shell-uart = &lpuart1; 32 }; 33 34 sdram0: memory@80000000 { 35 /* ISSI IS42S16160J-6TLI */ 36 device_type = "memory"; 37 reg = <0x80000000 DT_SIZE_M(32)>; 38 }; 39 40 leds { 41 compatible = "gpio-leds"; 42 green_led: led-1 { 43 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; 44 label = "User LD1"; 45 }; 46 }; 47 48 gpio_keys { 49 compatible = "gpio-keys"; 50 user_button: button-1 { 51 label = "User SW4"; 52 gpios = <&gpio5 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; 53 zephyr,code = <INPUT_KEY_0>; 54 }; 55 }; 56 57 arduino_header: connector { 58 compatible = "arduino-header-r3"; 59 #gpio-cells = <2>; 60 gpio-map-mask = <0xffffffff 0xffffffc0>; 61 gpio-map-pass-thru = <0 0x3f>; 62 gpio-map = <0 0 &gpio1 26 0>, /* A0 */ 63 <1 0 &gpio1 27 0>, /* A1 */ 64 <2 0 &gpio1 28 0>, /* A2 */ 65 <3 0 &gpio1 29 0>, /* A3 */ 66 <4 0 &gpio1 31 0>, /* A4 */ 67 <5 0 &gpio1 30 0>, /* A5 */ 68 <6 0 &gpio1 25 0>, /* D0 */ 69 <7 0 &gpio1 24 0>, /* D1 */ 70 <8 0 &gpio1 9 0>, /* D2 */ 71 <9 0 &gpio1 7 0>, /* D3 */ 72 <10 0 &gpio1 5 0>, /* D4 */ 73 <11 0 &gpio1 6 0>, /* D5 */ 74 <12 0 &gpio1 14 0>, /* D6 */ 75 <13 0 &gpio1 22 0>, /* D7 */ 76 <14 0 &gpio1 23 0>, /* D8 */ 77 <15 0 &gpio1 15 0>, /* D9 */ 78 <16 0 &gpio1 11 0>, /* D10 */ 79 <17 0 &gpio1 12 0>, /* D11 */ 80 <18 0 &gpio1 13 0>, /* D12 */ 81 <19 0 &gpio1 10 0>, /* D13 */ 82 <20 0 &gpio3 23 0>, /* D14 */ 83 <21 0 &gpio3 22 0>; /* D15 */ 84 }; 85}; 86 87arduino_serial: &lpuart2 { 88 pinctrl-0 = <&pinmux_lpuart2>; 89 pinctrl-1 = <&pinmux_lpuart2_sleep>; 90 pinctrl-names = "default", "sleep"; 91}; 92 93&flexspi { 94 status = "okay"; 95 reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; 96 is25wp064: is25wp064@0 { 97 compatible = "nxp,imx-flexspi-nor"; 98 size = <67108864>; 99 reg = <0>; 100 spi-max-frequency = <133000000>; 101 status = "okay"; 102 jedec-id = [9d 70 17]; 103 erase-block-size = <4096>; 104 write-block-size = <1>; 105 106 partitions { 107 compatible = "fixed-partitions"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 111 boot_partition: partition@0 { 112 label = "mcuboot"; 113 reg = <0x00000000 DT_SIZE_K(64)>; 114 }; 115 /* Note slot 0 has one additional sector, 116 * this is intended for use with the swap move algorithm 117 */ 118 slot0_partition: partition@10000 { 119 label = "image-0"; 120 reg = <0x00010000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; 121 }; 122 slot1_partition: partition@311000 { 123 label = "image-1"; 124 reg = <0x00311000 DT_SIZE_M(3)>; 125 }; 126 storage_partition: partition@611000 { 127 label = "storage"; 128 reg = <0x00611000 DT_SIZE_K(1980)>; 129 }; 130 }; 131 }; 132}; 133 134&lpi2c1 { 135 status = "okay"; 136 pinctrl-0 = <&pinmux_lpi2c1>; 137 pinctrl-names = "default"; 138}; 139 140&lpi2c4 { 141 status = "okay"; 142 pinctrl-0 = <&pinmux_lpi2c4>; 143 pinctrl-names = "default"; 144}; 145 146&lpuart1 { 147 status = "okay"; 148 current-speed = <115200>; 149 pinctrl-0 = <&pinmux_lpuart1>; 150 pinctrl-1 = <&pinmux_lpuart1_sleep>; 151 pinctrl-names = "default", "sleep"; 152}; 153 154&lpspi1 { 155 status = "okay"; 156 /* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */ 157 dmas = <&edma0 0 13>, <&edma0 1 14>; 158 dma-names = "rx", "tx"; 159 pinctrl-0 = <&pinmux_lpspi1>; 160 pinctrl-names = "default"; 161}; 162 163&enet { 164 status = "okay"; 165 pinctrl-0 = <&pinmux_enet>; 166 pinctrl-names = "default"; 167 int-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 168 reset-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; 169 ptp { 170 status = "okay"; 171 pinctrl-0 = <&pinmux_ptp>; 172 pinctrl-names = "default"; 173 }; 174}; 175 176zephyr_udc0: &usb1 { 177 status = "okay"; 178}; 179 180&usdhc1 { 181 status = "okay"; 182 no-1-8-v; 183 pinctrl-0 = <&pinmux_usdhc1>; 184 pinctrl-1 = <&pinmux_usdhc1_slow>; 185 pinctrl-2 = <&pinmux_usdhc1_med>; 186 pinctrl-3 = <&pinmux_usdhc1_fast>; 187 pinctrl-names = "default", "slow", "med", "fast"; 188 cd-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; 189 pwr-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 190 sdmmc { 191 compatible = "zephyr,sdmmc-disk"; 192 status = "okay"; 193 }; 194}; 195 196&adc1 { 197 status = "okay"; 198 pinctrl-0 = <&pinmux_adc1>; 199 pinctrl-names = "default"; 200}; 201 202&sai3 { 203 pinctrl-0 = <&pinmux_sai3>; 204 pinctrl-names = "default"; 205}; 206 207&edma0 { 208 status = "okay"; 209}; 210 211/* GPT and Systick are enabled. If power management is enabled, the GPT 212 * timer will be used instead of systick, as allows the core clock to 213 * be gated. 214 */ 215&gpt_hw_timer { 216 status = "okay"; 217}; 218 219&systick { 220 status = "okay"; 221}; 222