1# Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
2# SPDX-License-Identifier: Apache-2.0
3
4config RISCV_ISA_RV32I
5	bool
6	help
7	  RV32I Base Integer Instruction Set - 32bit
8
9config RISCV_ISA_RV32E
10	bool
11	help
12	  RV32E Base Integer Instruction Set (Embedded) - 32bit
13
14config RISCV_ISA_RV64I
15	bool
16	default y if 64BIT
17	help
18	  RV64I Base Integer Instruction Set - 64bit
19
20config RISCV_ISA_RV128I
21	bool
22	help
23	  RV128I Base Integer Instruction Set - 128bit
24
25config RISCV_ISA_EXT_M
26	bool
27	help
28	  (M) - Standard Extension for Integer Multiplication and Division
29
30	  Standard integer multiplication and division instruction extension,
31	  which is named "M" and contains instructions that multiply or divide
32	  values held in two integer registers.
33
34config RISCV_ISA_EXT_A
35	bool
36	help
37	  (A) - Standard Extension for Atomic Instructions
38
39	  The standard atomic instruction extension is denoted by instruction
40	  subset name "A", and contains instructions that atomically
41	  read-modify-write memory to support synchronization between multiple
42	  RISC-V threads running in the same memory space.
43
44config RISCV_ISA_EXT_F
45	bool
46	help
47	  (F) - Standard Extension for Single-Precision Floating-Point
48
49	  Standard instruction-set extension for single-precision
50	  floating-point, which is named "F" and adds single-precision
51	  floating-point computational instructions compliant with the IEEE
52	  754-2008 arithmetic standard.
53
54config RISCV_ISA_EXT_D
55	bool
56	depends on RISCV_ISA_EXT_F
57	help
58	  (D) - Standard Extension for Double-Precision Floating-Point
59
60	  Standard double-precision floating-point instruction-set extension,
61	  which is named "D" and adds double-precision floating-point
62	  computational instructions compliant with the IEEE 754-2008
63	  arithmetic standard.
64
65config RISCV_ISA_EXT_G
66	bool
67	select RISCV_ISA_EXT_M
68	select RISCV_ISA_EXT_A
69	select RISCV_ISA_EXT_F
70	select RISCV_ISA_EXT_D
71	select RISCV_ISA_EXT_ZICSR
72	select RISCV_ISA_EXT_ZIFENCEI
73	help
74	  (IMAFDZicsr_Zifencei) IMAFDZicsr_Zifencei extensions
75
76config RISCV_ISA_EXT_Q
77	bool
78	depends on RISCV_ISA_RV64I
79	depends on RISCV_ISA_EXT_F
80	depends on RISCV_ISA_EXT_D
81	help
82	  (Q) - Standard Extension for Quad-Precision Floating-Point
83
84	  Standard extension for 128-bit binary floating-point instructions
85	  compliant with the IEEE 754-2008 arithmetic standard. The 128-bit or
86	  quad-precision binary floatingpoint instruction subset is named "Q".
87
88config RISCV_ISA_EXT_C
89	bool
90	help
91	  (C) - Standard Extension for Compressed Instructions
92
93	  RISC-V standard compressed instruction set extension, named "C",
94	  which reduces static and dynamic code size by adding short 16-bit
95	  instruction encodings for common operations.
96
97config RISCV_ISA_EXT_ZICSR
98	bool
99	help
100	  (Zicsr) - Standard Extension for Control and Status Register (CSR) Instructions
101
102	  The "Zicsr" extension introduces support for the full set of CSR
103	  instructions that operate on CSRs registers.
104
105config RISCV_ISA_EXT_ZIFENCEI
106	bool
107	help
108	  (Zifencei) - Standard Extension for Instruction-Fetch Fence
109
110	  The "Zifencei" extension includes the FENCE.I instruction that
111	  provides explicit synchronization between writes to instruction
112	  memory and instruction fetches on the same hart.
113
114config RISCV_ISA_EXT_ZBA
115	bool
116	help
117	  (Zba) - Zba BitManip Extension
118
119	  The Zba instructions can be used to accelerate the generation of
120	  addresses that index into arrays of basic types (halfword, word,
121	  doubleword) using both unsigned word-sized and XLEN-sized indices: a
122	  shifted index is added to a base address.
123
124config RISCV_ISA_EXT_ZBB
125	bool
126	help
127	  (Zbb) - Zbb BitManip Extension (Basic bit-manipulation)
128
129	  The Zbb instructions can be used for basic bit-manipulation (logical
130	  with negate, count leading / trailing zero bits, count population,
131	  etc...).
132
133config RISCV_ISA_EXT_ZBC
134	bool
135	help
136	  (Zbc) - Zbc BitManip Extension (Carry-less multiplication)
137
138	  The Zbc instructions can be used for carry-less multiplication that
139	  is the multiplication in the polynomial ring over GF(2).
140
141config RISCV_ISA_EXT_ZBS
142	bool
143	help
144	  (Zbs) - Zbs BitManip Extension (Single-bit instructions)
145
146	  The Zbs instructions can be used for single-bit instructions that
147	  provide a mechanism to set, clear, invert, or extract a single bit in
148	  a register.
149