1# Memory Protection Unit (MPU) configuration options
2
3# Copyright (c) 2017 Linaro Limited
4# SPDX-License-Identifier: Apache-2.0
5
6if CPU_HAS_MPU
7
8config ARM_MPU
9	bool "ARM MPU Support"
10	select MPU
11	select SRAM_REGION_PERMISSIONS
12	select THREAD_STACK_INFO
13	select ARCH_HAS_EXECUTABLE_PAGE_BIT
14	select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if !(CPU_HAS_NXP_MPU || ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R)
15	select MPU_REQUIRES_NON_OVERLAPPING_REGIONS if CPU_HAS_ARM_MPU && (ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R)
16	select MPU_GAP_FILLING if AARCH32_ARMV8_R
17	help
18	  MCU implements Memory Protection Unit.
19
20	  Notes:
21	  The ARMv6-M and ARMv7-M MPU architecture requires a power-of-two
22	  alignment of MPU region base address and size.
23
24	  The NXP MPU as well as the ARMv8-M MPU do not require MPU regions
25	  to have power-of-two alignment for base address and region size.
26
27	  The ARMv8-M MPU requires the active MPU regions be non-overlapping.
28	  As a result of this, the ARMv8-M MPU needs to fully partition the
29	  memory map when programming dynamic memory regions (e.g. PRIV stack
30	  guard, user thread stack, and application memory domains), if the
31	  system requires PRIV access policy different from the access policy
32	  of the ARMv8-M background memory map. The application developer may
33	  enforce full PRIV (kernel) memory partition by enabling the
34	  CONFIG_MPU_GAP_FILLING option.
35	  By not enforcing full partition, MPU may leave part of kernel
36	  SRAM area covered only by the default ARMv8-M memory map. This
37	  is fine for User Mode, since the background ARM map does not
38	  allow nPRIV access at all. However, since the background map
39	  policy allows instruction fetches by privileged code, forcing
40	  this Kconfig option off prevents the system from directly
41	  triggering MemManage exceptions upon accidental attempts to
42	  execute code from SRAM in XIP builds.
43	  Since this does not compromise User Mode, we make the skipping
44	  of full partitioning the default behavior for the ARMv8-M MPU
45	  driver.
46
47config ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
48	int
49	default 256 if ARM_MPU && ARMV6_M_ARMV8_M_BASELINE && !ARMV8_M_BASELINE
50	default 64 if ARM_MPU && AARCH32_ARMV8_R
51	default 32 if ARM_MPU
52	default 4
53	help
54	  Minimum size (and alignment) of an ARM MPU region. Use this
55	  symbol to guarantee minimum size and alignment of MPU regions.
56	  A minimum 4-byte alignment is enforced in ARM builds without
57	  support for Memory Protection.
58
59if ARM_MPU
60
61config MPU_STACK_GUARD
62	bool "Thread Stack Guards"
63	help
64	  Enable Thread Stack Guards via MPU
65
66config MPU_STACK_GUARD_MIN_SIZE_FLOAT
67	int
68	depends on MPU_STACK_GUARD
69	depends on FPU_SHARING
70	default 128
71	help
72	  Minimum size (and alignment when applicable) of an ARM MPU
73	  region, which guards the stack of a thread that is using the
74	  Floating Point (FP) context. The width of the guard is set to
75	  128, to accommodate the length of a Cortex-M exception stack
76	  frame when the floating point context is active. The FP context
77	  is only stacked in sharing FP registers mode, therefore, the
78	  option is applicable only when FPU_SHARING is selected.
79
80config MPU_ALLOW_FLASH_WRITE
81	bool "Add MPU access to write to flash"
82	help
83	  Enable this to allow MPU RWX access to flash memory
84
85config MPU_DISABLE_BACKGROUND_MAP
86	bool "Disables the default background address map"
87	help
88	  Enable this to turn off the default background MPU address map. Your
89	  SoC definition should likely provide its own custom MPU regions.
90
91config CUSTOM_SECTION_ALIGN
92	bool "Custom Section Align"
93	help
94	  MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT(ARMv7-M) sometimes cause memory
95	  wasting in linker scripts defined memory sections. Use this symbol
96	  to guarantee user custom section align size to avoid more memory used
97	  for respect alignment. But that needs carefully configure MPU region
98	  and sub-regions(ARMv7-M) to cover this feature.
99
100config CUSTOM_SECTION_MIN_ALIGN_SIZE
101	int "Custom Section Align Size"
102	default 32
103	help
104	  Custom align size of memory section in linker scripts. Usually
105	  it should consume less alignment memory. Although this alignment
106	  size is configured by users, it must also respect the power of
107	  two regulation if hardware requires.
108
109endif # ARM_MPU
110
111endif # CPU_HAS_MPU
112