1 /*
2  * Copyright (c) 2021 NXP
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <zephyr/arch/xtensa/irq.h>
8 #include <zephyr/device.h>
9 #include <xtensa/xtruntime.h>
10 #include <zephyr/irq_nextlevel.h>
11 #include <xtensa/hal.h>
12 #include <zephyr/init.h>
13 
14 #include "soc.h"
15 
16 #ifdef CONFIG_DYNAMIC_INTERRUPTS
17 #include <zephyr/sw_isr_table.h>
18 #endif
19 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
20 #include <zephyr/logging/log.h>
21 LOG_MODULE_REGISTER(soc);
22 
z_soc_irq_enable(uint32_t irq)23 void z_soc_irq_enable(uint32_t irq)
24 {
25 	/*
26 	 * enable core interrupt
27 	 */
28 	z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
29 }
30 
z_soc_irq_disable(uint32_t irq)31 void z_soc_irq_disable(uint32_t irq)
32 {
33 	/*
34 	 * disable the interrupt in interrupt controller
35 	 */
36 	z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
37 }
38 
z_soc_irq_is_enabled(unsigned int irq)39 int z_soc_irq_is_enabled(unsigned int irq)
40 {
41 	int ret = 0;
42 
43 	/* regular interrupt */
44 	ret = z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
45 
46 	return ret;
47 }
48